Patents by Inventor John V. Veliadis

John V. Veliadis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190131480
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: NARSINGH B. SINGH, JOHN V. VELIADIS, BETTINA NECHAY, ANDRE BERGHMANS, DAVID J. KNUTESON, DAVID KAHLER, BRIAN WAGNER, MARC SHERWIN
  • Patent number: 10211359
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 19, 2019
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
  • Patent number: 9960159
    Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 1, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20170194527
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Application
    Filed: November 18, 2016
    Publication date: July 6, 2017
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: NARSINGH B. SINGH, JOHN V. VELIADIS, BETTINA NECHAY, ANDRE BERGHMANS, DAVID J. KNUTESON, DAVID KAHLER, BRIAN WAGNER, MARC SHERWIN
  • Patent number: 9570646
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 14, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
  • Publication number: 20160155738
    Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: JOHN V. VELIADIS
  • Patent number: 9293465
    Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 22, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20160079244
    Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: JOHN V. VELIADIS
  • Publication number: 20150236186
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: NARSINGH B. SINGH, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
  • Patent number: 8958193
    Abstract: A system/method for providing an optically triggered circuit breaker is provided. The system comprises a junction field-effect transistor (JFET) and gate drive coupled to the JFET's gate. The gate drive applies voltage bias (VG) to the gate and the gate drive is configured to bias VG so that the system allows current flow through the JFET in the Drain to Source or Source to Drain directions, or so that the system blocks voltages applied to the Drain and/or Source. The system also comprises a photodetector which detects light emitted by the JFET resulting from a fault condition. The photodetector transmits a signal to the gate drive to provide the selectively biased VG so that the system blocks voltages applied to the Drain and/or Source, in response to the light detection. A system/method for providing an optically triggered bidirectional circuit breaker comprising common source JFETs and two photodetectors is alternatively provided.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 17, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20140268465
    Abstract: A system/method for providing an optically triggered circuit breaker is provided. The system comprises a junction field-effect transistor (JFET) and gate drive coupled to the JFET's gate. The gate drive applies voltage bias (VG) to the gate and the gate drive is configured to bias VG so that the system allows current flow through the JFET in the Drain to Source or Source to Drain directions, or so that the system blocks voltages applied to the Drain and/or Source. The system also comprises a photodetector which detects light emitted by the JFET resulting from a fault condition. The photodetector transmits a signal to the gate drive to provide the selectively biased VG so that the system blocks voltages applied to the Drain and/or Source, in response to the light detection. A system/method for providing an optically triggered bidirectional circuit breaker comprising common source JFETs and two photodetectors is alternatively provided.
    Type: Application
    Filed: July 31, 2013
    Publication date: September 18, 2014
    Applicant: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8829573
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 9, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20140175460
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 26, 2014
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: John V. Veliadis
  • Patent number: 8735227
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 27, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20140106517
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: John V. Veliadis
  • Patent number: 8664048
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: March 4, 2014
    Assignee: Northrop Grummen Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8283749
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 9, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20120161208
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 28, 2012
    Applicant: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20120104416
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Application
    Filed: January 5, 2012
    Publication date: May 3, 2012
    Applicant: Northrop Grumman Systems Corporation
    Inventor: John V. VELIADIS
  • Patent number: 8130023
    Abstract: A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D1 and D2), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (VG) to both the gates. The gate drive is configured to selectively bias VG so that current flows through the VJFETs in the D1 to D2 direction, flows through the VJFETs in the D2 to D1 direction or voltages applied to D1 of the first VJFET or D2 of the second VJFET are blocked.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis