Abstract: A digital to analog converter (“DAC”) (20). The DAC includes an input (23) for receiving a plurality of successive digital words (D3−D0), and circuitry (28, 30) for storing the plurality of successive digital words. The DAC also includes a string (12′) of series connected resistive elements, wherein the string comprises a plurality of voltage taps (T0′-T15′). The DAC further includes an output (OUTA) for providing an analog output voltage corresponding to a selected one of the plurality of successive digital words. The DAC further includes comparison circuitry (32) for comparing the selected one and an earlier received one of the plurality of successive digital words. Finally, the DAC includes circuitry (34, 24, 26) for generating the analog output voltage in response to the comparison circuitry.

Abstract: A data converter (20) comprising an input (I0′-I2′) for receiving an input signal and an output (VOUT′) for providing an output signal formed in response to the input signal. The converter also includes a string of series-connected resistive elements (12′) having in total a string resistance (DENOM) and providing a plurality of voltage taps (T0′-T7′), wherein at least one of the voltage taps is accessible in response to the input signal and for forming the output signal. The converter further includes a calibration circuit (22). The calibration circuit includes a plurality of trimming transistors (TT0-TT6) connected in parallel to selected ones of the plurality of voltage taps. Each of the trimming transistors has an adjustable resistance.

Abstract: An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor manufacturing process flow. A spiral conductor with square windings is formed in metal layer (20) patterned so that straight runs of successive turns (22, 23, 24) overlie corresponding runs of concentric square rings (16, 17, 18) formed in underlying metal layer (14). A unity gain voltage buffer (30) connects each ring (16, 17, 18) with a respective overlying turn (22, 23, 24).

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: A voltage-controlled oscillator (10), which is comprised of two subcircuits (10a, 10b). Each subcircuit (10a, 10b) has a pair of differentially connected transistors (Q1,Q2 and Q3,Q4). The first subcircuit (10a) is an LC oscillation subcircuit, in which each transistor (Q1, Q2) has a capacitive transformer (C11,C12 and C21,C22) in its feedback loop. The second subcircuit (10b) is a current-controlled variable-capacitance subcircuit, whose feedback loop has a gain that determines the effective capacitance of the subcircuit (10b). When the subcircuits (10a, 10b) are combined, the feedback loops on each side of the differential pairs (Q1,Q2 and Q3,Q4) share the capacitive transformer (C11,C12 and C21,C22). The result is that the effective capacitance determines the oscillation frequency for the oscillator (10).

Abstract: Inclusion of a current mirror circuit and differential amplifier in the input amplifier stage 10 and a current mirror circuit in the feed-forward amplifier stage 12 of the nested transconductance capacitance compensation multistage amplifier design provides a low-voltage multistage amplifier having less sensitivity to power supply voltage while retaining frequency domain advantages. The nested transconductance capacitance compensation multistage amplifier includes an input differential amplifier stage 10, a feed-forward amplifier stage 12, and an output amplifier stage 14. This design improves the power supply rejection of the multistage operational amplifier.

Abstract: A data converter (20) comprising an input (I.sub.0 '-I.sub.3 ') for receiving a digital word and an output (V.sub.OUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0'-BL3') formed with an alignment in a first dimension and a plurality of word lines formed (WL0'-WL3') with an alignment in a second dimension different than the first dimension. Still further, the data converter comprises a string (12') comprising a plurality of series connected resistive elements (R10-R24) and a plurality of voltage taps (T10-T25), where at least a majority of the plurality of series connected resistive elements are formed with an alignment in the second dimension. Lastly, the data converter comprises a plurality of switching transistors (ST10-ST25) coupled between the plurality of voltage taps and the output.

Abstract: A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60).

Abstract: The invention is a power conserving clock driver circuit operative where a differential pair of clock (clock+ and clock-) signals are desired. The circuit responds to transitions in both clock signals to turn off the clock driver transistors (M1P,M1N) (M2N, M2P) for a period of time. During that period of time, a pass gate configuration (M3N, M3P) is conductive. When this occurs, the charge on one of the capacitive loads C.sub.L1 or C.sub.L2 is transferred through the inductor L.sub.c. In this fashion, part of the charge on one of the capacitive loads is transferred directly to the other capacitive load thereby conserving power. The time period during which this power transfer occurs is the time for one half cycle at the natural resonant frequency of the circuit comprised of L.sub.c, C.sub.L1 and C.sub.L2.

Abstract: A regulated cascode circuit with enhanced gain includes a cascode section including a common source MOS transistor (m.sub.1) of a first polarity and a cascode device (m.sub.2) wherein the drain of the common-source MOS transistor (m.sub.1) is coupled to the source of the cascode device. An input to the regulated cascode circuit is applied to the common source MOS transistor (m.sub.1) and an output of the regulated cascode circuit is developed at the drain of the cascode device (m.sub.2) across both the common source MOS transistor (m.sub.1) and cascode (m.sub.2) device. A feedback amplifier circuit (10) has its input (12) connected to the drain of the common source MOS transistor (m.sub.1) and its output (20) connected to a gate of the cascode device (m.sub.2) for driving the cascode device (m.sub.2). The feedback amplifier (10) includes a simple five transistor circuit.

Abstract: Voltage minimizer and maximizer circuits are provided for both single-ended and fully-differential analog input voltages. A single-ended analog voltage maximizer circuit includes a plurality of operational amplifiers (OP.sub.1, OP.sub.2 . . . OP.sub.N) wherein the number of operational amplifiers corresponds to the number of separate voltages (V.sub.1, V.sub.2 . . . V.sub.N) from which a maximum voltage is to be determined, each of the operational amplifiers receives a single-ended analog voltage at its non-inverting input, each output of the plurality of operational amplifiers is connected to a common output line where the maximum analog voltage output (V.sub.0) will be received, the common output line is also connected to the inverting input of each of the operational amplifiers. Each operational amplifier also has an operational amplifier circuit (FIGS.

Abstract: A variable frequency oscillator (19) and method of producing an oscillating signal are provided in which a current mirror (12) receives a control current and generates a mirrored current. A capacitor (20) is coupled to the current mirror (12) and charges and discharges through the current mirror (12) based on the direction of the mirrored current. A trigger (22) is coupled to the capacitor (20) and outputs a first voltage level when the capacitor (20) charges to a first voltage threshold and outputs a second voltage level when the capacitor (20) discharges to a second voltage threshold. A switch (14) is coupled to the current mirror (12) and the trigger (22) for changing the direction of the mirrored current based on the output voltage of the trigger (22).

Abstract: A second order sigma delta modulator (10) includes a digital to analog converter (26) that provides feedback for system modulation. The digital to analog converter (26) employs a dynamic element matching circuit (72) which randomly selects among main capacitors (C.sub.j) to reduce the effect of capacitor value mismatching. The digital to analog converter (26) also employs a self calibration circuit (80) to trim the values of the main capacitors (C.sub.j) to obtain better capacitor matching. During self calibration, a clock signal (f.sub.rand) driving a pseudo random number generator (74) of the dynamic element matching circuit (72) is reduced to assist in minimizing variance in a digital output signal for accurate calibration of the main capacitors (C.sub.j). Upon completion of calibration, the clock signal (f.sub.rand) is returned to a frequency coinciding with the modulator clock rate.

Abstract: This dielectric relaxation correction circuit for charge-redistribution A/D converters, which has a comparator 20 and operates in a sample, hold and conversion mode, comprises: a capacitor array 22, a replica capacitance 35, having a bottom plate, arranged so as to be subject to the same sequence of charging voltages that the array capacitors 22 experience but in a neutralizing manner such that an error in the capacitor array 22 voltage is neutralized by the same error in the replica capacitance 35, and; a sample and hold circuit (S/H) 36 for sampling an input signal voltage during the sample mode, wherein the sample and hold 36 is arranged to hold the bottom plate of the replica capacitance 35 at the input signal voltage. Other devices, systems and methods are also disclosed.

Abstract: An amplification circuit in accordance with the present invention includes an amplifier comprising four inputs. Each of the four inputs is operable to receive a respective analog signal and a respective DC bias signal. Also included is supply circuitry for providing a first and second controlled DC bias signal. Each of the DC bias signals is operable to couple to selected ones of the four inputs of the amplifier.

Abstract: An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

Abstract: A common-mode feedback circuit comprises a reference generator (12) for generating a signal corresponding to a desired common-mode operating point connected to a common-mode bias circuit (14) for generating a second signal corresponding to the common-mode operating point of the outputs (V.sub.out.sup.+, V.sub.out.sup.-) of the fully differential operational amplifier. In the preferred embodiment, the common-mode bias circuit (14) includes a sensing circuit (58) comprising two MOS transistors (60, 62) having sources and drains connected together. The MOS transistors (60, 62) operate in the ohmic region to provide a variable load responsive to the output signals (V.sub.out.sup.+, V.sub.out.sup.-) connected to their gates.

Abstract: A multistage comparison circuit (10) having a cascaded chain of capacitively coupled comparators (34) is disclosed. A reset mode of operation (54) imposes a common mode voltage on the input of the comparators (34). Consequently, capacitors (22, 24) which couple the comparators (34) together are charged to compensate for errors so that a high precision comparison may result. A shorting switch (40) couples across differential outputs (36, 38) of the comparators (34) and is momentarily activated prior to each bit comparison (71) in a word comparison mode (70) of operation. This shorting takes the comparators (34) out of saturation and places the comparison circuit (10) in a state which approximates the reset state. Specific comparator architectures are disclosed which force approximately equal currents to be fed into the output nodes (36, 38) and which dynamically adjust output offset voltage and feedthrough errors so that the shorted condition accurately approximates the reset condition.