Patents by Inventor John W. Golz

John W. Golz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9870979
    Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
  • Patent number: 9559040
    Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
  • Patent number: 9543229
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9536809
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20150371927
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Application
    Filed: August 30, 2015
    Publication date: December 24, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, JR., Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20150364401
    Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Inventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
  • Publication number: 20150187642
    Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
  • Publication number: 20150187733
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
  • Patent number: 7046572
    Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: May 16, 2006
    Assignee: International Business Machines Corporation
    Inventors: David R. Hansen, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
  • Patent number: 7023758
    Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: April 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: David R. Hanson, Gregory J Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
  • Patent number: 6845033
    Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: January 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Kirihata, John W. Golz
  • Publication number: 20040252573
    Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Applicant: International Business Machine Corporation
    Inventors: David R. Hanson, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
  • Publication number: 20040240246
    Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Inventors: John W. Golz, David R. Hanson, Hoki Kim
  • Patent number: 6816397
    Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: John W. Golz, David R. Hanson, Hoki Kim
  • Publication number: 20040174733
    Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 9, 2004
    Applicant: International Business Machines Corporation
    Inventors: Toshiaki Kirihata, John W Golz
  • Patent number: 6768143
    Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, John W. Golz, David R. Hanson, Hoki Kim
  • Patent number: 6747890
    Abstract: Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: June 8, 2004
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Kirihata, Subramanian S. Iyer, John W. Golz
  • Patent number: 6303275
    Abstract: A method of forming a resist layer of uniform thickness across a surface patterned with a varying density of high aspect ratio features. A selected material layer having an affinity to a resist coat to be applied over the selected material layer is applied to a wafer having a plurality of recesses before applying a resist coat. After the resist coat is applied over the selected material layer, the selected material diffuses partially into the resist coat to condition a portion of the resist coat to be insoluble in the presence of a developer which is applied after the resist coat. Those portions of the resist coat into which the selected material layer has not diffused then are removed by a developer leaving a uniform resist coat thickness across the wafer.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: October 16, 2001
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Coles, John W. Golz, Qinghuang Lin, Alan C. Thomas, Christopher J. Waskiewicz, Teresa J. Wu
  • Patent number: 6294449
    Abstract: A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: September 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Teresa J. Wu, Bomy A. Chen, John W. Golz, Charles W. Koburger, III, Paul C. Parries, Christopher J. Waskiewicz, Jin Jwang Wu