Abstract: A video display is provided with a planar piezoelectric transmitter to transmit ultrasound signals, and a display panel including a plurality of pixels. Each pixel has a data interface to accept a video signal with a variable voltage associated with a range of light intensity values, and to supply a touch signal with a variable voltage derived from a range of reflected ultrasound signal energies. Each pixel is made up of a light device to supply light with an intensity responsive to the video signal voltage, and a storage capacitor to maintain a video signal voltage between refresh cycles. A piezoelectric transducer accepts a reflected ultrasound signal energy and maintains a touch signal voltage between refresh cycles. In one aspect, the storage capacitor and the piezoelectric transducer are the same device. The light device may be a liquid crystal (LC) layer or a light emitting diode.

Abstract: A method of performing a fluid-material assay employing a device including at least one active pixel having a sensor with an assay site functionalized for selected fluid-assay material. The method includes exposing the pixel's sensor assay site to such material, and in conjunction with such exposing, and employing the active nature of the pixel, remotely requesting from the pixel's sensor assay site an assay-result output report. The method further includes, in relation to the employing step, creating, relative to the sensor's assay site in the at least one pixel, a predetermined, pixel-specific electromagnetic field environment.

Abstract: A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.

Abstract: A digitally-addressable, pixelated, DNA fluid-assay, active-matrix micro-structure formed, utilizing low-temperature TFT and Si technology, on a substrate preferably made of glass or plastic, and including at least one pixel which is defined by (a) an addressable pixel site, (b) a sensor home structure disposed within that site for receiving and hosting a functionalized assay site possessing a DNA oligonucleotide probe, and (c) an addressable, pixel-site-specific, energy-field-producing functionalizer (preferably optical) operable to functionalize such a probe on the assay site. Each pixel may also include a pixel-integrated optical detector. Further disclosed are related methodology facets involving (1) the making of such a micro-structure (a) in a precursor form (without a functionalized probe), and thereafter (b) in a finalized/functionalized form (with such a probe), and (2) the ultimate use of a completed micro-structure in the performance of a DNA assay.

Abstract: A method of producing a precursor, active-matrix, fluid-assay micro-structure including the steps of (1) utilizing low-temperature TFT and Si technology, establishing preferably on a glass or plastic substrate a matrix array of non-functionalized pixels, and (2) preparing at least one of these pixels for individual, digitally-addressed (a) functionalization, and (b) reading out, ultimately, of completed assay results.

Abstract: A pixel-by-pixel digitally-addressable, pixelated, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one functionalized, digitally-addressable assay sensor including at least one functionalized, digitally-addressable assay site which has been affinity-functionalized to respond to a selected, specific fluid-assay material, and (b) disposed operatively adjacent that sensor and its associated assay site, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the sensor and its associated assay site, a selected, ambient, electromagnetic field environment which is structured to assist, selectively and optionally only, in the reading-out of an assay-result response from the assay sensor and assay site.

Abstract: A method for producing an active-matrix, fluid-assay micro-structure including, utilizing low-temperature TFT and Si technology, establishing preferably on a glass or plastic substrate a matrix array of digitally-addressable, assay-material-specific-functionalizable pixels, and employing pixel-specific digital addressing for selected, array-established pixels, individually functionalizing these pixels.

Abstract: A method of performing a fluid-material assay employing a device including at least one active pixel having a sensor with an assay site functionalized for selected fluid-assay material. The method includes exposing the pixel's sensor assay site to such material, and in conjunction with such exposing, and employing the active nature of the pixel, remotely requesting from the pixel's sensor assay site an assay-result output report. The method further includes, in relation to the employing step, creating, relative to the sensor's assay site in the at least one pixel, a predetermined, pixel-specific electromagnetic field environment.

Abstract: A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.

Abstract: A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.

Abstract: A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.

Abstract: A high-density plasma method is provided for forming a SiOXNY thin-film. The method provides a substrate and introduces a silicon (Si) precursor. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a SiOXNY thin-film is formed, where (X+Y<2 and Y>0). The SiOXNY thin-film can be stoichiometric or non-stoichiometric. The SiOXNY thin-film can be graded, meaning the values of X and Y vary with the thickness of the SiOXNY thin-film. Further, the process enables the in-situ deposition of a SiOXNY thin-film multilayer structure, where the different layers may be stoichiometric, non-stoichiometric, graded, and combinations of the above-mentioned types of SiOXNY thin-films.

Abstract: A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: A non-stoichiometric SiOXNY thin-film optical filter is provided. The filter is formed from a substrate and a first non-stoichiometric SiOX1NY1 thin-film overlying the substrate, where (X1+Y1<2 and Y1>0). The first non-stoichiometric SiOX1NY1 thin-film has a refractive index (n1) in the range of about 1.46 to 3, and complex refractive index (N1=n1+ik1), where k1 is an extinction coefficient in a range of about 0 to 0.5. The first non-stoichiometric SiOX1NY1 thin-film may be either intrinsic or doped. In one aspect, the first non-stoichiometric SiOX1NY1 thin-film has nanoparticles with a size in the range of about 1 to 10 nm. A second non-stoichiometric SiOX2NY2 thin-film may overlie the first non-stoichiometric SiOX1NY1 thin-film, where Y1?Y2. The second non-stoichiometric SiOX1NY1 thin-film may be intrinsic and doped. In another variation, a stoichiometric SiOX2NY2 thin-film, intrinsic or doped, overlies the first non-stoichiometric SiOX1NY1 thin-film.

Abstract: A method is provided for additionally oxidizing a thin-film oxide. The method includes: providing a substrate; depositing an MyOx (M oxide) layer overlying the substrate, where M is a solid element having an oxidation state in a range of +2 to +5; treating the MyOx layer to a high density plasma (HDP) source; and, forming an MyOk layer in response to the HDP source, where k>x. In one aspect, the method further includes decreasing the concentration of oxide charge in response to forming the MyOk layer. In another aspect, the MyOx layer is deposited with an impurity N, and the method further includes creating volatile N oxides in response to forming the MyOk layer. For example, the impurity N may be carbon and the method creates a volatile carbon oxide.

Abstract: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.