Abstract: A dynamic random access memory device stores two bits of digital data in each memory cell. Two sense amplifiers are provided to sense and reproduce any of the four binary values 11, 10, 01, 00 representing a strong one, a weak one, a weak zero and a strong zero, respectively, capable of being stored in each cell. The signal read out of a memory cell is restored to the memory cell by a feedback circuit which utilizes the outputs of the sense amplifiers. Thus the proper charge is replaced on the selected storage capacitor in the memory cell.

Abstract: A dynamic random access memory device stores two bits of digital data in each memory cell. Two sense amplifiers are provided to sense and reproduce any of the four binary values 11, 10, 01, 00 representing a strong one, a weak one, a weak zero and a strong zero, respectively, capable of being stored in each cell. The signal read out of a memory cell is restored to the memory cell by a feedback circuit which utilizes the outputs of the sense amplifiers. Thus the proper charge is replaced on the selected storage capacitor in the memory cell.

Abstract: A dynamic random access memory device stores two bits of digital data in each memory cell. Two sense amplifiers are provided to sense and reproduce any of the four binary values 11, 10, 01, 00 representing a strong one, a weak one, a weak zero and a strong zero, respectively, capable of being stored in each cell. The signal read out of a memory cell is restored to the memory cell by a feedback circuit which utilizes the outputs of the sense amplifiers. Thus the proper charge is replaced on the selected storage capacitor in the memory cell.

Abstract: The device and method of the present invention characterizes a telephone call by identifying a code, comparing the code to a predetermined access/ID code and generating a signal in response to the code. The device provides called party identification, calling party identification, and telephone number identification.

Abstract: An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

Abstract: A sense amplifier for determining the binary logic state of a dynamic memory cell (11.sub.x,y) preamplifies an initial voltage difference established between a first input line (17.sub.y) coupled to the memory cell (11.sub.x,y) and a first reference line (18.sub.y) coupled to a reference cell (32.sub.y). The resulting amplifies voltage difference is generated between a second input line (19) coupled through a coupling device (Q51.sub.y) to the first input line (17.sub.y) and a second reference line (20) coupled through another coupling device (Q52.sub.y) to the first reference line (18.sub.y) by capacitively charging the second lines (19 and 20) preferably with a pair of capacitors (C61 and C62) individually coupled to the second lines (19 and 20). A differential sensing device (90) senses the amplified voltage difference to determine the logic state which is fully restored to the memory cell (11.sub.x,y).

Abstract: A voltage protection circuit for controlling an input data signal on a signal-carrying line to a binary data-storage device having an input line for receiving the input data signal comprises two transistors in series having current-control electrodes coupled to an input control terminal and a third transistor having its current-control electrode coupled to the input line with one current-conducting electrode coupled to a voltage source and another current-conducting electrode coupled to current-conducting electrodes of the first two transistors.

Abstract: A high-performance address buffer for use with a dynamic random-access memory is transistor-transistor logic-input compatible, utilizing a time constant on which activation of one output is dependent.