Abstract: A memory cell in an EPROM device which is totally sealed from ultraviolet light by a conductive cover without openings therein for leads to the cell's drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N+ implants, buried N+ layers or N-wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N+ implant or N-well serves as the control gate and is capacitvely coupled to the floating gate via a thin oxide layer in a coupling area.

Abstract: A CMOS fabrication process for EEPROMs having high-breakdown-voltage peripheral transistors in which a single implant step early in the process forms buried implants for both the memory cell's tunnel area source and the high voltage transistor's source and drain areas. The single implant step can be formed either before or after the formation of the channel stops and field oxide around the devices. The floating gate of the memory cell and the gates of the other devices are formed with polysilicon, the gates of the high voltage transistor overlapping the buried implants of its source and drain. The sources and drains of the other peripheral devices are then formed, using their polysilicon gates as a self-aligning mask. This may also include the formation of contact source and drain for the high voltage transistor. The process concludes with the formation of one or two layers of conductive lines connecting to specified drains, sources and gates to form a desired circuit pattern.

Abstract: An EEPROM fabrication process using N-well CMOS technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high-temperature drive-in and oxidation cycle with a 1000 .ANG. to 2500 .ANG. thick nitride mask covering device areas. The floating gate stack with tunneling window is formed by implanting a first species of N-type impurity, forming a first gate oxide layer, defining a window in the oxide layer over the implant, implanting a second species of N-type impurity through the window, regrowing a thin oxide layer 70 .ANG. to 90 .ANG. thick in a window, depositing a first polysilicon layer having a thickness of between 2500 .ANG. and 3400 .ANG., selectively removing the polysilicon and gate oxide layers to form a floating gate, growing a uniformly thick second oxide layer at 1,000.degree. to 1,050.degree. C.