Abstract: A state control circuit gives an inactive state control signal to a CPU and an active state control signal to a data transmission circuit. In response to this, the CPU goes into the halt state and the data transmission circuit goes into the receive state. When receive processing is completed, the state control circuit gives an active state control signal to the CPU. In response to this, the CPU restores from the halt state to the operative state. The CPU gives an instruction signal to the state control circuit. The state control circuit gives an inactive state control signal to the data transmission circuit. In response to this, the data transmission circuit goes into the halt state.

Abstract: A state control circuit (107) gives an inactive state control signal (S2) to a CPU (105) and an active state control signal (S3) to a data transmission circuit (102). In response to this, the CPU (105) goes into the halt state and the data transmission circuit (102) goes into the receive state. When receive processing is completed, the state control circuit (107) gives an active state control signal (S2) to the CPU (105). In response to this, the CPU (105) restores from the halt state to the operative state. The CPU (105) gives an instruction signal (CMD2) to the state control circuit (107). The state control circuit (107) gives an inactive state control signal (S3) to the data transmission circuit (102). In response to this, the data transmission circuit (102) goes into the halt state.

Abstract: The present invention provides an IC card and an IC card utilization system, which are excellent in security. An IC card 100 comprises a microcomputer 102 having a program processor 104 for executing a program, a ROM 101 for containing an encrypted program executed by the program processor 104, a key storage unit 105 for containing a secret key, and a cipher decoder 103 for decoding the encrypted program from the ROM 101 using the secret key from the key storage unit 105 and giving the decoded program to the program processor 104.

Abstract: In the semiconductor integrated circuit device of the present invention which includes at least one dynamic circuit having one or more floating gates in a static state, a switching circuit is provided either between the floating gate and a power source or between the floating gate and the ground which is driven by a clock signal input to the dynamic circuit and sets the potential of the floating gate at a predetermined value in the static state of the dynamic circuit.

Abstract: Provided are a row address circuit for driving all word lines at one time so as to select all memory cells in a memory circuit when receiving a writing control signal for test and a column address circuit for writing some particular pattern of test data which corresponds to a data specifying signal into the memory cells at one time via all pairs of bit lines when receiving the writing control signal. Also, provided in the memory circuit is a test circuit for judging at one time whether the data held in each memory cell conforms with an expected value thereof. Thus a time required for testing a semiconductor memory device of a large capacity is reduced.

Abstract: An internal bus test circuit for testing an integrated circuit internal bus which interconnects a plurality of function modules of the integrated circuit, the test circuit including switches that are operable for isolating respective modules from the bus, a bus setting circuit enabling individual lines to the bus to be set to a desired logic level, and a by-pass bus with corresponding by-pass circuits, for a function module that is connected between the bus and external pads. The test circuit thereby enables the bus functions to be easily tested in real-time operation, independently of the respective conditions of the test modules that are connected to the bus.

Abstract: Disclosed is a semiconductor memory device having a circuit integrally comprising both functions as the sense amplifier circuit for operating when reading out data from the memory cell and as the drive circuit for operating when writing data into the memory cell. By such structure, fast and stable operation of the semiconductor memory device is realized, and the area of the portions corresponding to the sense amplifier circuit and drive circuit can be reduced, so that higher density and higher degree of integration of semiconductor memory device may be realized.

Abstract: A cell containing a test pad is defined as a standard cell, in the same fashion as a logic circuit, and is disposed and wired, together with logic circuit cells, in the internal circuit region excluding the input and output pad regions around the chip by a standard cell system. The cell containing the test pad possesses the pad region for feeding a reference potential in the cell, or the pad region capable of detecting a reference signal, or the layout pattern for expressing an arbitrary code for distinguishing the cell from other cells.

Abstract: Method for measuring power supply current, e.g., standby current of a random access memory in which, before starting measurement of the power supply current, data is read-out from memory cell of the random access memory and opposite data is written in the memory cell so that the random access memory enters into an unstabilized state. By use of this method, the measurement of the maximum power supply current can be conducted precisely.