Patents by Inventor Jon S. Martens

Jon S. Martens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6882160
    Abstract: Techniques are provided for performing full N-port calibrations in an environment in which a test set is used to connect an N-port DUT to an M-port VNA, where N>M. Techniques for incorporating port impedances as part of a calibration sequence are provided. Also provided are techniques for using sequential characterization and de-embedding to generate virtual calibrations that are then used in a renormalization process.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: April 19, 2005
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, David V. Judge, Jimmy A. Bigelow
  • Publication number: 20040251922
    Abstract: Techniques are provided for performing full N-port calibrations in an environment in which a test set is used to connect an N-port DUT to an M-port VNA, where N>M. Techniques for incorporating port impedances as part of a calibration sequence are provided. Also provided are techniques for using sequential characterization and de-embedding to generate virtual calibrations that are then used in a renormalization process.
    Type: Application
    Filed: November 5, 2003
    Publication date: December 16, 2004
    Applicant: Anritsu Company
    Inventors: Jon S. Martens, David V. Judge, Jimmy A. Bigelow
  • Patent number: 6832170
    Abstract: Methods are provided for embedding and/or de-embedding a network having an even number of ports into a device under test (DUT) having an odd number of ports. For example, a four-port network can be embedded/de-embedded into/from a three-port device under test (DUT). This is accomplished by embedding a virtual circulator into the three-port DUT to thereby generate an artificial four-port device. The four-port network is then embedded/de-embedded into/from the artificial four-port device to thereby generate a composite four-port device. The virtual circulator is then de-embedded from the composite four-port device to thereby generate a composite three-port device that is equivalent to the four-port network embedded/de-embedded into/from the three-port DUT.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: December 14, 2004
    Assignee: Anritsu Company
    Inventor: Jon S. Martens
  • Publication number: 20040153265
    Abstract: Methods, systems and computer program products for efficiently characterizing devices under test (DUTs) using a vector network analyzer (VNA) are provided. A N-port DUT can be divided as appropriate into multiple sub-devices, or multiple separate devices can be present. A parent calibration is performed. The VNA is then used to determine the S-parameters of interest for each sub-device or separate device, preferably without measuring S-parameters that are not of interest. This can include measuring S-parameters and removing corresponding error coefficients determined during the parent calibration.
    Type: Application
    Filed: August 15, 2003
    Publication date: August 5, 2004
    Applicant: Anritsu Company
    Inventors: Jon S. Martens, Rena Ho, Jamie Tu
  • Patent number: 6766262
    Abstract: Methods for determining a corrected intermodulation distortion (IMD) product measurement for a device under test (DUT) are provided. A ratioed receiver IMD product is measured, where the receiver IMD product results from non-linearities in a receiver. Next, a ratioed composite IMD product is measured, where the composite IMD product results from non-linearities in both the receiver and the DUT. The corrected DUT IMD product (DUTP) can then be determined by subtracting the ratioed receiver IMD product from the ratioed composite IMD product to remove the effects of IMD due to the receiver.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: July 20, 2004
    Assignee: Anritsu Company
    Inventor: Jon S. Martens
  • Patent number: 6665628
    Abstract: Methods are provided for virtually embedding and/or de-embedding balanced four-port networks into/from a device under test (DUT). For the methods, a set of scattering-parameters is acquired for the DUT. Additionally, a respective set of scatter-parameters is acquired for each of the balanced four-port networks to be embedded and/or de-embedded. A transfer-matrix is generating for the DUT based on its scattering parameters. Further, a respective transfer-matrix is generated for each of the networks to be embedded/de-embedded based on its respective set of scattering-parameters. The transfer-matrix for the DUT is then multiplied with the one or more transfer-matrices associated with the balanced four-port networks to be embedded and/or by an inverse of the transfer-matrices associated with the balanced four-port networks to be de-embedded. A composite transfer-matrix is thereby produced. Finally, a set of composite scattering-parameters is then generated based on the composite transfer-matrix.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: December 16, 2003
    Assignee: Anritsu Company
    Inventor: Jon S. Martens
  • Publication number: 20030222652
    Abstract: Methods for determining a corrected intermodulation distortion (IMD) product measurement for a device under test (DUT) are provided. A ratioed receiver IMD product is measured, where the receiver IMD product results from non-linearities in a receiver. Next, a ratioed composite IMD product is measured, where the composite IMD product results from non-linearities in both the receiver and the DUT. The corrected DUT IMD product (DUTP) can then be determined by subtracting the ratioed receiver IMD product from the ratioed composite IMD product to remove the effects of IMD due to the receiver.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventor: Jon S. Martens
  • Patent number: 6650123
    Abstract: Methods are provided for characterizing N interface devices (e.g., adapters or test fixture arms) using a vector network analyzer (VNA). These N interface devices are useful for connecting an N-port device under test (DUT) to the VNA. A first step of includes performing an N-port calibration at each of N outer reference planes. A second step includes performing an N-port calibration at each of N inner reference planes. A set of scattering-parameters (S-parameters) is then determined for each of the N interface devices based on results of the calibrations performed at the first step and results of the calibrations performed at the second step. Each set of S-parameters characterizes a respective one of the N interface devices.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: November 18, 2003
    Assignee: Anritsu Company
    Inventor: Jon S. Martens
  • Publication number: 20030208327
    Abstract: Methods are provided for embedding and/or de-embedding a network having an even number of ports into a device under test (DUT) having an odd number of ports. For example, a four-port network can be embedded/de-embedded into/from a three-port device under test (DUT). This is accomplished by embedding a virtual circulator into the three-port DUT to thereby generate an artificial four-port device. The four-port network is then embedded/de-embedded into/from the artificial four-port device to thereby generate a composite four-port device. The virtual circulator is then de-embedded from the composite four-port device to thereby generate a composite three-port device that is equivalent to the four-port network embedded/de-embedded into/from the three-port DUT.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventor: Jon S. Martens
  • Publication number: 20030135344
    Abstract: Methods are provided for virtually embedding and/or de-embedding balanced four-port networks into/from a device under test (DUT). For the methods, a set of scattering-parameters is acquired for the DUT. Additionally, a respective set of scatter-parameters is acquired for each of the balanced four-port networks to be embedded and/or de-embedded. A transfer-matrix is generating for the DUT based on its scattering parameters. Further, a respective transfer-matrix is generated for each of the networks to be embedded/de-embedded based on its respective set of scattering-parameters. The transfer-matrix for the DUT is then multiplied with the one or more transfer-matrices associated with the balanced four-port networks to be embedded and/or by an inverse of the transfer-matrices associated with the balanced four-port networks to be de-embedded. A composite transfer-matrix is thereby produced. Finally, a set of composite scattering-parameters is then generated based on the composite transfer-matrix.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 17, 2003
    Inventor: Jon S. Martens
  • Publication number: 20030132758
    Abstract: Methods are provided for characterizing N interface devices (e.g., adapters or test fixture arms) using a vector network analyzer (VNA). These N interface devices are useful for connecting an N-port device under test (DUT) to the VNA. A first step of includes performing an N-port calibration at each of N outer reference planes. A second step includes performing an N-port calibration at each of N inner reference planes. A set of scattering-parameters (S-parameters) is then determined for each of the N interface devices based on results of the calibrations performed at the first step and results of the calibrations performed at the second step. Each set of S-parameters characterizes a respective one of the N interface devices.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 17, 2003
    Inventor: Jon S. Martens
  • Publication number: 20020196033
    Abstract: An S-parameter measurement technique allows measurement of devices under test (DUTs), such as power amplifiers, which require a modulated power tone drive signal for proper biasing, in combination with a probe tone test signal, wherein both the modulated and probe tone signals operate in the same frequency range. The technique uses a stochastic drive signal, such as a CDMA or WCDMA modulated signal in combination with a low power probe tone signal. A receiver in a VNA having a significantly narrower bandwidth than the modulated signal bandwidth enables separation of the modulated and probe tone signals. VNA calibration further improves the measurement accuracy. For modulated signals with a significant power level in the frequency range of the probe tone signal, ensemble averaging of the composite probe tone and power tone signals is used to enable separation of the probe tone signal for measurement.
    Type: Application
    Filed: May 2, 2002
    Publication date: December 26, 2002
    Inventor: Jon S. Martens
  • Patent number: 5440238
    Abstract: Apparatus and method for detecting, determining, and imaging surface resistance corrosion, thin film growth, and oxide formation on the surface of conductors or other electrical surface modification. The invention comprises a modified confocal resonator structure with the sample remote from the radiating mirror. Surface resistance is determined by analyzing and imaging reflected microwaves; imaging reveals anomalies due to surface impurities, non-stoichiometry, and the like, in the surface of the superconductor, conductor, dielectric, or semiconductor.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: August 8, 1995
    Assignee: Sandia Corporation
    Inventors: Jon S. Martens, David S. Ginley, Vincent M. Hietala, Neil R. Sorensen
  • Patent number: 5411937
    Abstract: A novel method for fabricating nanometer geometry electronic devices is described. Such Josephson junctions can be accurately and reproducibly manufactured employing photolithographic and direct write electron beam lithography techniques in combination with aqueous etchants. In particular, a method is described for manufacturing planar Josephson junctions from high temperature superconducting material.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: May 2, 1995
    Assignee: Sandia Corporation
    Inventors: Joel R. Wendt, Thomas A. Plut, Jon S. Martens
  • Patent number: 5389837
    Abstract: A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.
    Type: Grant
    Filed: April 21, 1993
    Date of Patent: February 14, 1995
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Vincent M. Hietala, Jon S. Martens, Thomas E. Zipperian
  • Patent number: 5378999
    Abstract: The present invention comprises a novel matrix amplifier. The matrix amplifier includes an active superconducting power divider (ASPD) having N output ports; N distributed amplifiers each operatively connected to one of the N output ports of the ASPD; and a power combiner having N input ports each operatively connected to one of the N distributed amplifiers. The distributed amplifier can included M stages of amplification by cascading superconducting active devices. The power combiner can include N active elements. The resulting (N.times.M) matrix amplifier can produce signals of high output power, large bandwidth, and low noise.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: January 3, 1995
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Jon S. Martens, Vincent M. Hietala, Thomas A. Plut
  • Patent number: 5358928
    Abstract: A process for formulating non-hysteretic and hysteretic Josephson junctions using HTS materials which results in junctions having the ability to operate at high temperatures while maintaining high uniformity and quality. The non-hysteretic Josephson junction is formed by step-etching a LaAlO.sub.3 crystal substrate and then depositing a thin film of TlCaBaCuO on the substrate, covering the step, and forming a grain boundary at the step and a subsequent Josephson junction. Once the non-hysteretic junction is formed the next step to form the hysteretic Josephson junction is to add capacitance to the system. In the current embodiment, this is accomplished by adding a thin dielectric layer, LaA1O.sub.3, followed by a cap layer of a normal metal where the cap layer is formed by first depositing a thin layer of titanium (Ti) followed by a layer of gold (Au). The dielectric layer and the normal metal cap are patterned to the desired geometry.
    Type: Grant
    Filed: September 22, 1992
    Date of Patent: October 25, 1994
    Assignee: Sandia Corporation
    Inventors: David S. Ginley, Vincent M. Hietala, Gert K. G. Hohenwarter, Jon S. Martens, Thomas A. Plut, Chris P. Tigges, Gregory A. Vawter, Thomas E. Zipperian
  • Patent number: 5350739
    Abstract: A HTS switch includes a HTS conductor for providing a superconducting path for an electrical signal and an serpentine wire actuator for controllably heating a portion of the conductor sufficiently to cause that portion to have normal, and not superconducting, resistivity. Mass of the portion is reduced to decrease switching time.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: September 27, 1994
    Assignee: The United States of America as repesented by the United States Department of Energy
    Inventors: Jon S. Martens, Vincent M. Hietala, Gert K. G. Hohenwarter
  • Patent number: 5262395
    Abstract: A transimpedance amplifier for use with high temperature superconducting, other superconducting, and conventional semiconductor allows for appropriate signal amplification and impedance matching to processing electronics. The amplifier incorporates the superconducting flux flow transistor into a differential amplifier configuration which allows for operation over a wide temperature range, and is characterized by high gain, relatively low noise, and response times less than 200 picoseconds over at least a 10-80 K. temperature range. The invention is particularly useful when a signal derived from either far-IR focal plane detectors or from Josephson junctions is to be processed by higher signal/higher impedance electronics, such as conventional semiconductor technology.
    Type: Grant
    Filed: March 12, 1992
    Date of Patent: November 16, 1993
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: David S. Ginley, Vincent M. Hietala, Jon S. Martens
  • Patent number: 5239269
    Abstract: Apparatus and method for determining and imaging superconductor surface resistance. The apparatus comprises modified Gaussian confocal resonator structure with the sample remote from the radiating mirror. Surface resistance is determined by analyzing and imaging reflected microwaves; imaging reveals anomalies due to surface impurities, non-stoichiometry, and the like, in the surface of the superconductor.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: August 24, 1993
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Jon S. Martens, Vincent M. Hietala, Gert K. G. Hohenwarter