Patents by Inventor Jonathan D. Reid

Jonathan D. Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9045840
    Abstract: Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, and an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating. The anode chamber may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the anode chamber and the ionically resistive ionically permeable element during electroplating. The anode chamber may include an insulating shield oriented between the anode and the ionically resistive ionically permeable element, with opening in a central region of the insulating shield.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 2, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: David W. Porter, Jonathan D. Reid, Frederick D. Wilmot
  • Publication number: 20150072538
    Abstract: Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal oxide surface on a substrate is reduced. A remote plasma apparatus can treat the metal oxide surface as well as cool, load/unload, and move the substrate within a single standalone apparatus. The remote plasma apparatus includes a processing chamber and a controller configured to provide a substrate having a metal seed layer in a processing chamber, move the substrate towards a substrate support in the processing chamber, form a remote plasma of a reducing gas species, expose a metal seed layer of the substrate to the remote plasma, and expose the substrate to a cooling gas. In some embodiments, the remote plasma apparatus is part of an electroplating apparatus.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Inventors: Tighe A. Spurlin, James E. Duncan, Stephen Lau, Marshall Stowell, Jonathan D. Reid, David Porter
  • Publication number: 20150053565
    Abstract: The embodiments herein relate to methods and apparatus for filling features with copper by a bottom-up fill mechanism without the use of organic plating additives. In some cases, filling occurs directly on a semi-noble metal layer, without the deposition of a copper seed layer. In other cases, the filling occurs on a copper seed layer. Factors such as the polarization of electrolyte, the use of a complexing agent, electrolyte pH, electrolyte temperature, and the waveform used to deposit material may contribute to promoting the bottom-up fill.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Lam Research Corporation
    Inventors: Huanfeng Zhu, Jonathan D. Reid
  • Publication number: 20140256128
    Abstract: Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal oxide surface on a substrate can be reduced to pure metal and the metal reflowed. A remote plasma apparatus can treat the metal oxide surface as well as cool, load/unload, and move the substrate within a single standalone apparatus. The remote plasma apparatus includes a processing chamber and a controller configured to provide a substrate having a metal seed layer in a processing chamber, form a remote plasma of a reducing gas species where the remote plasma includes radicals, ions, and/or ultraviolet (UV) radiation from the reducing gas species, and expose a metal seed layer of the substrate to the remote plasma to reduce oxide of the metal seed layer to metal and to reflow the metal.
    Type: Application
    Filed: November 21, 2013
    Publication date: September 11, 2014
    Inventors: Tighe A. Spurlin, George Andrew Antonelli, Natalia Doubina, James E. Duncan, Jonathan D. Reid, David Porter
  • Publication number: 20140199497
    Abstract: Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. Metal oxide surfaces are reduced to form a film integrated with a metal seed layer by contacting a solution with a reducing agent with the metal oxide surfaces. The solution with the reducing agent can contact the metal oxide surfaces under conditions that form an integrated film with the metal seed layer, and that reduces reoxidation from exposure the ambient environment. In some embodiments, an additive can be included with the reducing agent to form a surface protecting layer on the metal seed layer. In some embodiments, the metal is copper used in damascene copper structures.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Inventors: Tighe A. Spurlin, Steven T. Mayer, Jonathan D. Reid, Artur Kolics, Huanfeng Zhu
  • Publication number: 20140138239
    Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.
    Type: Application
    Filed: October 10, 2013
    Publication date: May 22, 2014
    Inventors: Jonathan D. Reid, Huanfeng Zhu
  • Patent number: 8722539
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 13, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
  • Publication number: 20140124361
    Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 8, 2014
    Applicant: Lam Research Corporation
    Inventors: Jonathan D. Reid, Huanfeng Zhu
  • Patent number: 8703615
    Abstract: Disclosed are methods of depositing and annealing a copper seed layer. A copper seed layer may be deposited on a ruthenium layer disposed on a surface of a wafer and on features in the wafer. The thickness of the ruthenium layer may be about 40 Angstroms or less. The copper seed layer may be annealed in a reducing atmosphere having an oxygen concentration of about 2 parts per million or less. Annealing the copper seed layer in a low-oxygen atmosphere may improve the properties of the copper seed layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer, Huanfeng Zhu
  • Patent number: 8623193
    Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: January 7, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T Mayer, Jonathan D. Reid
  • Patent number: 8575028
    Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: November 5, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Huanfeng Zhu
  • Publication number: 20130284604
    Abstract: Apparatus and methods for electroplating metal onto substrates are disclosed. The electroplating apparatus comprise an electroplating cell and at least one oxidization device. The electroplating cell comprises a cathode chamber and an anode chamber separated by a porous barrier that allows metal cations to pass through but prevents organic particles from crossing. The oxidation device (ODD) is configured to oxidize cations of the metal to be electroplated onto the substrate, which cations are present in the anolyte during electroplating. In some embodiments, the ODD is implemented as a carbon anode that removes Cu(I) from the anolyte electrochemically. In other embodiments, the ODD is implemented as an oxygenation device (OGD) or an impressed current cathodic protection anode (ICCP anode), both of which increase oxygen concentration in anolyte solutions. Methods for efficient electroplating are also disclosed.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 31, 2013
    Inventors: Tighe A. Spurlin, Charles L. Merrill, Ludan Huang, Matthew Thorum, Lee Brogan, James E. Duncan, Frederick D. Wilmot, Marshall R. Stowell, Steven T. Mayer, Haiying Fu, David W. Porter, Shantinath Ghongadi, Jonathan D. Reid, Hyosang S. Lee, Mark J. Willey
  • Patent number: 8513124
    Abstract: Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 20, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer
  • Publication number: 20130137242
    Abstract: Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 30, 2013
    Inventors: Zhian HE, David W. PORTER, Jonathan D. REID, Frederick D. WILMOT
  • Publication number: 20130134045
    Abstract: Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, and an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating. The anode chamber may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the anode chamber and the ionically resistive ionically permeable element during electroplating. The anode chamber may include an insulating shield oriented between the anode and the ionically resistive ionically permeable element, with opening in a central region of the insulating shield.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Inventors: David W. PORTER, Jonathan D. REID, Frederick D. WILMOT
  • Patent number: 8415261
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: April 9, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Publication number: 20120261254
    Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.
    Type: Application
    Filed: May 16, 2011
    Publication date: October 18, 2012
    Inventors: Jonathan D. REID, Huanfeng ZHU
  • Publication number: 20120264290
    Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.
    Type: Application
    Filed: May 16, 2011
    Publication date: October 18, 2012
    Inventors: Jonathan D. REID, Huanfeng ZHU
  • Patent number: 8268155
    Abstract: Methods, electroplating solution, and apparatuses for electroplating copper into a surface of a partially fabricated semiconductor substrate are provided. Electroplating solutions include copper ions, suppressor additives, chloride ions, and alternative halide ions, which include bromide ions and/or iodide ions. The concentration of the alternative halide ions in the solution may be between about 0.25 ppm and 20 ppm. Addition of the alternative halide ions at certain concentrations improves suppression properties of the solution over a range of feature sizes without a need to change suppressors.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: September 18, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Jian Zhou, Jonathan D. Reid
  • Publication number: 20120181170
    Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.
    Type: Application
    Filed: March 28, 2012
    Publication date: July 19, 2012
    Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida