Patents by Inventor Jonathan D. Reid

Jonathan D. Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6214193
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: April 10, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Patent number: 6162344
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: December 19, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 6110346
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: August 29, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 6099702
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 8, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Patent number: 6074544
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: June 13, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 5421507
    Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au--Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: June 6, 1995
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Davis, Richard Hsiao, James R. Loomis, Jae M. Park, Jonathan D. Reid
  • Patent number: 5280414
    Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: January 18, 1994
    Assignee: International Business Machines Corp.
    Inventors: Charles R. Davis, Richard Hsiao, James R. Loomis, Jae M. Park, Jonathan D. Reid
  • Patent number: 5153986
    Abstract: Disclosed is a method of fabricating a multilayer electronic circuit package. The multilayer circuit package has at least one layer that is a circuitized, polymer encapsulated metal core. According to the method of the invention a metal foil is provided for the metal core of the layer. This metal core foil may be provided as a single unit or in a continuous, roll to roll, process. The vias and through holes are drilled, etched, or punched through the metal foil. An adhesion promoter is then applied to the perforate metal foil for subsequent adhesion of polymer to the foil. The dielectric polymer is then applied to the perforate metal foil core by vapor depositing, chemical vapor depositing, spraying or electrophoretically depositing, a thermally processable dielectric polymer or precursor thereof onto exposed surfaces of the perforate metal foil including the walls of the through holes and vias.
    Type: Grant
    Filed: July 17, 1991
    Date of Patent: October 13, 1992
    Assignee: International Business Machines
    Inventors: John M. Brauer, Frederick R. Christie, William H. Lawrence, Ashit A. Mehta, Jonathan D. Reid, William J. Summa
  • Patent number: 4969979
    Abstract: Substantially nonconductive or semiconductive surfaces of through holes can be electroplated directly, without an intervening non-electrolytic metallization, by a stepwise process which includes the application to the through holes of a polyelectrolyte surfactant in solution in combination with the application of a conductive metal containing material.
    Type: Grant
    Filed: May 8, 1989
    Date of Patent: November 13, 1990
    Assignee: International Business Machines Corporation
    Inventors: Bernd K. Appelt, Perminder Bindra, Robert D. Edwards, James R. Loomis, Jae M. Park, Jonathan D. Reid, Lisa J. Smith, James R. White
  • Patent number: 4904350
    Abstract: According to the present invention, a submersible electrical current supply device and method of plating using said device for providing electrical current to a strip as it is continuously moved through an electroplating bath is provided. The electrical current supply device includes a housing having a slot extending therethrough with entry and exit openings and has wipers disposed at both the entrance and exit openings. In the central section of the device, electrical contacts in the form of electrical brushes are biased into contact with the strip and are provided with electrical contacts to supply current for plating to the brushes. The strip is continuously passed through the slot and contact with the brushes and electrical current is supplied by the brushes.
    Type: Grant
    Filed: November 14, 1988
    Date of Patent: February 27, 1990
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Reid, Eugene P. Skarvinko, Arthur G. Starks