Abstract: Drivers which control hardware devices in a network adapter chip are disabled prior to reducing power to a first portion of circuits in the network adapter chip. Power is received by a second portion of circuits which are utilized for detecting network activity and communicating the activity to processors. Upon network activity detection, the first portion of circuits receives power. Drivers are enabled subsequent to detection. Drivers are enabled after receiving power by the first portion of circuits. Processors control hardware devices, disable devices before power reduction, enable devices after network activity detection and enable devices after receiving power. The network adapter chip is reset for power reception. A power reduction mode is selected where drivers are disabled after reducing power. Drivers are enabled after hardware devices are enabled. A first state is characterized by no signal before disabling drivers. A second state is characterized by signal detection before receiving power.

Abstract: Certain embodiments of a cable sense mode for intelligent power saving in the absence of a link pulse may include detecting an energy level of an Ethernet link. The Ethernet link may couple a network adapter chip to a network. The power supplied to the network adapter chip may be adjusted based on the detected energy level. Power may be supplied to the network adapter chip if the detected energy level of the Ethernet link is greater than or equal to a particular energy level. Power may be reduced to the network adapter chip if the detected energy level of the Ethernet link is less than a particular energy level. An output signal and/or an interrupt signal may be generated that indicates a change in the detected energy level of the Ethernet link. Power may be provided to the circuitry that generates the output signal and the interrupt signal.

Abstract: Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

Abstract: Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: Certain embodiments of an extreme power down mode for extreme power savings when no network presence is detected may comprise disabling at least one device driver for at least one hardware device in a network adapter chip. The device driver may be disabled prior to disabling the hardware device upon starting a power reduction mode for the network adapter chip. The device driver for the hardware device on the network adapter chip may be enabled after enabling the hardware device upon ending a power reduction mode for the network adapter chip. The hardware device may be disabled by reducing power to it. Similarly, power may be provided to the hardware device to enable it. The network adapter chip may be reset to enable the hardware device upon providing power to the hardware device so that the hardware device may be at a known state.

Abstract: Drivers which control hardware devices in a network adapter chip are disabled prior to reducing power to a first portion of circuits in the network adapter chip. Power is received by a second portion of circuits which are utilized for detecting network activity and communicating the activity to processors. Upon network activity detection, the first portion of circuits receives power. Drivers are enabled subsequent to detection. Drivers are enabled after receiving power by the first portion of circuits. Processors control hardware devices, disable devices before power reduction, enable devices after network activity detection and enable devices after receiving power. The network adapter chip is reset for power reception. A power reduction mode is selected where drivers are disabled after reducing power. Drivers are enabled after hardware devices are enabled. A first state is characterized by no signal before disabling drivers. A second state is characterized by signal detection before receiving power.

Abstract: Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

Abstract: Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

Abstract: Certain embodiments for a self-booting Ethernet controller chip (NAC) may comprise a processor within the NAC that determines whether legacy boot code is present in memory external to the NAC. If legacy boot code is present in the external memory, the NAC may boot from the legacy boot code. If the legacy boot code is not present in the external memory, the processor may boot the NAC from the self-boot code in the ROM within the NAC. The processor may also read network configuration data from the external memory. The network configuration data may be stored, for example, in a NVRAM. The processor may copy the network configuration data from the NVRAM to a RAM within the NAC while booting.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.

Abstract: Certain embodiments for modifying operation of ROM based boot code may include modifying a bootup sequence for boot code resident in a ROM within a network adapter chip (NAC). The bootup sequence may be modified during booting of the NAC using code patches in memory external to the NAC. The boot code may comprise ROM loader code and/or self-boot code in the ROM within the NAC. Execution of the self-boot code may comprise execution of code patches. The code patches may comprise initialization code patches and service code patches. The code patches may be executed in place of functions in the self-boot code or in addition to the functions in the self-boot code. Additionally, the code patches may be configured such that a function in the self-boot code may be effectively deleted where no corresponding code patch may be executed in place of the function.

Abstract: Methods and systems for fast Ethernet controller operation using a virtual CPU are disclosed and may comprise controlling an on-chip Ethernet controller utilizing a virtual CPU comprising a microcode engine that loads a single instruction and executes the instruction prior to loading or executing a subsequent instruction. The instructions may be fetched by the virtual CPU from an external non-volatile memory or on-chip ROM. The virtual CPU may initialize the Ethernet controller and provide patches for supporting hardware workarounds, wake on LAN service, and vital production data such as serial number, product name, manufacturer and related manufacturing data. The virtual CPU may power down the Ethernet controller and may be halted via a particular command and procedure.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: Automatically detecting types of external FLASH devices is provided, and may comprise communicating one or more read memory device ID commands corresponding to at least one supported memory device to at least one memory device. Data received in response to this communication may be utilized to determine whether the received data identifies the memory device as one of the plurality of supported memory devices. The supported memory devices may be serial FLASH memory devices. Each read memory device ID command may be manufacturer specific, or may be specific to a group of the supported memory devices. The communicating of read memory device ID commands and determining whether the memory device is a supported memory device may be repeated if the memory device is not identified as one of the supported memory devices. There may be a limit to the number of times this is repeated.