Abstract: A system for powering up an electronic circuit with telephone line power such that the electronic circuit does not enter a lockup state. The system includes a voltage detector that measures the voltage across the telephone line and a switch coupled with the voltage detector. The voltage detector generates a Reset signal when the measured voltage exceeds a selected voltage level, and the switch applies power to the electronic circuit in response to the generated Reset signal.

Abstract: An ADSL front end is implemented with an adaptive AM interference canceller to cancel out either a carrier signal of an interfering AM radio signal, or a carrier signal and its sidebands of an interfering AM radio signal, from a received ADSL signal. By canceling an interfering AM radio signal rather than simply filtering out the relevant interfered with frequency band, the interfered with frequency band remains useable for ADSL transmission. In one embodiment, a reference AM radio receiver is either fixedly or adaptively tuned to the carrier frequency of an interfering AM radio station, and the received signal in the frequency band surrounding that carrier frequency is digitized and provided to an adaptive interference canceller. The adaptive interference canceller adaptively adjusts a time delay and phase of the generated AM interference signal to optimize cancellation at a hybrid of the same AM radio signal received as interference over a subscriber line.

Abstract: A method and apparatus for a telephone line interface or data access arrangement (DAA) which includes a shunt regulator in series with a line modulator. A sense resistor is placed in series between the shunt regulator and the line modulator to provide a measurement of the amount of current distortion in the DAA. The line modulator contains a Darlington pair which reduces the amount of current drawn by the line modulator, allowing the sense resistor to sense a majority of the system current. The voltage across the sense resistor is fed back to the line modulator. The line modulator is capable of adjusting the AC modulation and the DC termination presented to the telephone line. The method includes drawing power from the telephone line using a shunt regulator, modulating the telephone line in series with the shunt regulator, sensing a level of distortion in the DAA, and feeding the sensed level of distortion to the line modulator.

Abstract: A method and apparatus for a data access arrangement (DAA) which includes a line modulator containing capacitive elements to increase system stability. The invention provides improved stability during system startup and normal system operation. The line modulator is capable of adjusting the AC modulation and the DC termination presented to the telephone line. Capacitive elements are added to the modulator to provide enhanced system stability. The method includes drawing power from the telephone line, modulating the telephone line, sensing a level of distortion through the line modulator, feeding the sensed level of distortion to the line modulator, and using capacitive circuits to provide additional system stability.

Abstract: The digital-to-analog converter includes an output line, and a plurality of converters receiving control signals representative of digital data. Each converter selectively connects the output line to a voltage in response to a respective one of the control signals. Optionally, the digital-to-analog converter further includes a reset circuit for resetting the voltage on the output line to a reset voltage between portions of the analog waveform representing a digital data symbol.

Abstract: A digital device for controlling the DC line current on a telephone line which includes a digital device that utilizes a digital filter for setting the DC line current. By controlling the DC line current digitally, software can be used to set the DC line current in accordance with predefined characteristics. Predefined characteristics can be set to accommodate varying country specifications instead of using switches to control resistors and capacitors. In addition, changes in a country's requirements can be accomplished through software, instead of changing components or redesigning a circuit board. The device also incorporates a method for maintaining DC current level during changes in digital filter characteristics. The use of software results in increased flexibility by allowing an infinite number of settings via software or software updates, and allowing changes to be made quickly and easily throughout the world.

Abstract: A method and apparatus for a telephone line interface or data access arrangement (DAA) which includes a shunt regulator in series with a line modulator. A first sense resistor is placed in series between the shunt regulator and the line modulator to provide a measurement of the amount of current distortion in the DAA shunt regulator. The voltage across the first sense resistor is fed back to the line modulator. A second sense resistor is inserted into the line modulator circuitry to provide a measurement of the system current distortion that is outside of the path containing the sense resistor used to monitor the current distortion in the DAA shunt regulator. The voltage across the second sense resistor is also fed back to the line modulator. The line modulator is capable of adjusting the AC modulation and the DC termination presented to the telephone line.

Abstract: A method and apparatus for transmitting and receiving digital data in a noisy environment. Digital data is transmitted with a degree of noise immunity by generating and transmitting a reference signal along with the transmitted digital data signal. The reference signal has a voltage level between a logic level low and a logic level high of the digital data signal. The reference signal can be used to identify the center point of the transmitting device logic levels. Furthermore, the reference signal allows the receiver to track and compensate for noise introduced at the transmitter of the digital data signal.

Abstract: A circuit provides a modulation signal to an input terminal of a line modulator which places a line current modulated in accordance with the modulation signal on a telephone line. An amplifier of the circuit amplifies an analog input signal to provide the modulation signal at an output terminal. A first resistor and a first capacitor are coupled in series between a first input terminal of the amplifier and the line, and a second resistor and a second capacitor are coupled in series between a second input terminal of the amplifier and the line. First and second precharge amplifiers are used to precharge the first and second capacitors, respectively, to reduce DC setup time.

Abstract: The digital-to-analog converter includes an output line, and a plurality of converters receiving control signals representative of digital data. Each converter selectively connects the output line to a voltage in response to a respective one of the control signals. Optionally, the digital-to-analog converter further includes a reset circuit for resetting the voltage on the output line to a reset voltage between portions of the analog waveform representing a digital data symbol.

Abstract: A method and apparatus for controlling the DC line current on a telephone line and reducing the amount of error introduced to the system. The error is reduced by compensating for a DC error term introduced by an analog to digital converter having a DC offset. The DC offset is controlled digitally, allowing software to be used to limit the DC error in accordance with predefined parameters. Predefined parameters can be set to accommodate varying country specifications instead of using switches to control resistors and capacitors. In addition, changes in a country's requirements can be accomplished through software, instead of changing components or redesigning a circuit board. The use of software results in increased flexibility by allowing an infinite number of settings via software or software updates, allowing changes to be made quickly and easily throughout the world, and allowing error terms to be accommodated digitally.

Abstract: A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator circuit are referred to ground to reduce the total DC current draw, e.g., by a factor of 7. The multiple use of the input stage bias and grounded connections to the positive and/or negative inputs reduce the overall current requirements of the differential comparator circuit substantially while maintaining full operating speed as compared to conventional differential comparator circuits. In one embodiment using the low power differential comparator circuit, a clock receiver implements hysteresis which is relatively independent from variations in environmental factors such as temperature, and from power supply variations. In this embodiment, the input stage of a low power comparator circuit is biased by the output of a bias circuit.

Abstract: A network interface circuit employing differentially driven capacitive couplings across a high voltage isolation boundary and in which a &Sgr;/&Dgr; CODEC is positioned on the line side of the high voltage interface. In this manner, only four wires cross the high voltage boundary, namely differential pairs for transmit data and receive data. The transfer functions for setting AC and DC parameters, such as impedance matching, are provided by digital filters. Further, with the CODEC on the line side of the high voltage isolation interface, the data which crosses the interface is modulated at the &Sgr;/&Dgr; data rate and, thus, capacitive coupling can be used across the high voltage isolation boundary without the loss of DC data.

Abstract: An ADSL front end is implemented with an adaptive AM interference canceller to cancel out either a carrier signal of an interfering AM radio signal, or a carrier signal and its sidebands of an interfering AM radio signal, from a received ADSL signal. By canceling an interfering AM radio signal rather than simply filtering out the relevant interfered with frequency band, the interfered with frequency band remains useable for ADSL transmission. In one embodiment, a reference AM radio receiver is either fixedly or adaptively tuned to the carrier frequency of an interfering AM radio station, and the received signal in the frequency band surrounding that carrier frequency is digitized and provided to an adaptive interference canceller. The adaptive interference canceller adaptively adjusts a time delay and phase of the generated AM interference signal to optimize cancellation at a hybrid of the same AM radio signal received as interference over a subscriber line.

Abstract: A network interface circuit employing differentially driven capacitive couplings across a high voltage isolation boundary and in which a &Sgr;/&Dgr; CODEC is positioned on the line side of the high voltage interface. In this manner, only four wires cross the high voltage boundary, namely differential pairs for transmit data and receive data. The transfer functions for setting AC and DC parameters, such as impedance matching, are provided by digital filters. Further, with the CODEC on the line side of the high voltage isolation interface, the data which crosses the interface is modulated at the &Sgr;/&Dgr; data rate and, thus, capacitive coupling can be used across the high voltage isolation boundary without the loss of DC data.

Abstract: An improvement to split-architecture audio codecs such as those defined by the Audio Codec '97 specification (AC '97) includes a simulated analog-to-digital (A/D) digitization of the PC beep signal from a personal computer (PC). A PC beep simulated A/D digitization circuit simulates the A/D conversion of the PC beep signal. The PC beep simulated A/D digitization circuit eliminates the need for a pre-amplifier, and reduces the design complexity and power consumption otherwise necessary for an A/D converter, by outputting either of two simulated A/D converter values corresponding respectively to a conversion of the HIGH and LOW logic levels of the PC beep signal. The simulated A/D converter output signal from the PC beep simulated digitization circuit is subsequently scaled and summed with the digital signals from other audio sources, and output from the audio codec.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: An integrated circuit including a DC sensing power-up reset (PUR) circuit and method for generating a reset signal. The PUR circuit comprises a first terminal for receiving a supply voltage and a second terminal for receiving a reference voltage corresponding to a low logic state. A first transistor is coupled between the first terminal and a first node, wherein the first transistor switches on when the supply voltage is rising and exceeds a rising trip point voltage. A second transistor is coupled between the first terminal and the first node, and switches off when the supply voltage falls below a falling trip point voltage which is less than the rising trip point voltage. A first inverter is coupled at an input terminal to the first node and at an output terminal to a second node. A resistor is coupled between the first node and the second terminal.

Abstract: A network interface circuit employs an extended feedback circuit topology for impedance matching across a high voltage boundary between a line side portion and low voltage portion of a network. The network interface circuit includes an operational amplifier-based circuit which is responsive to a signal applied from user equipment on the low voltage portion. Specifically, the present invention includes a transmit path having a first, second, and third amplifier circuit and an impedance element, and a receive path that includes a transfer function implemented as a second order low pass filter for correcting amplifier gain and phase effects in the complex feedback loop of the circuit. The output impedance is remotely set by multiplying the impedance element by a scale factor to match the network impedance. The feedback loop is extended across the high voltage boundary using high voltage interfaces such as linear optical coupling devices (LOCs).

Abstract: An integrated circuit, e.g. an Audio Codec (AC) '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a direct current (DC) buildup at internal nodes. The IIR filter performs a plurality of 2.sup.nd order biquadratic equations in an overall average of as few as four clock cycles per 2.sup.