Patents by Inventor Jonathan J. Wierer

Jonathan J. Wierer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734553
    Abstract: A light emitting device is described. The light emitting device includes a substrate and a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region and has a first surface adjacent the substrate and a second surface opposite the first surface. The first surface of the semiconductor structure multiple cavities formed therein, which extend into at least one of the n-type region and the p-type region. The cavities are spaced apart and lined by a dielectric layer. At least a portion of the second surface is roughened to form multiple features spaced apart at a distance smaller than a distance between each of the cavities formed in the first surface to enhance extraction of light emitted from the light emitting layer. At least one contact is disposed between the first surface of the semiconductor structure and the substrate.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 4, 2020
    Assignee: Lumileds LLC
    Inventors: Jonathan J. Wierer, Aurelien Jean Francois David, Henry Kwong-Hin Choy
  • Patent number: 10672949
    Abstract: A device comprising a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is disclosed. The device comprises a porous region. The device comprises a first layer disposed between the light emitting layer and the porous region. The device comprises a mask layer disposed between the porous region and the first layer. The device comprises a plurality of openings formed in the mask layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 2, 2020
    Assignee: Lumileds LLC
    Inventors: Jonathan J. Wierer, John E. Epler
  • Patent number: 10553767
    Abstract: An LED subpixel can be provided with a reflector layer that controls viewing angles. After formation of an array of nanowires including first conductivity type cores and active layers, a second conductivity type semiconductor material layer, a transparent conductive oxide layer, and a dielectric material layer are sequentially formed. An opening is formed through the dielectric material layer over the array of nanowires. The reflector layer can be formed around the array of nanowires and through the opening in the dielectric material layer on the transparent conductive oxide layer. A conductive bonding structure is formed in electrical contact with the reflector layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 4, 2020
    Assignee: GLO AB
    Inventors: Fariba Danesh, Nathan F. Gardner, Jonathan J. Wierer, Jr.
  • Publication number: 20190280161
    Abstract: A light emitting device is described. The light emitting device includes a substrate and a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region and has a first surface adjacent the substrate and a second surface opposite the first surface. The first surface of the semiconductor structure multiple cavities formed therein, which extend into at least one of the n-type region and the p-type region. The cavities are spaced apart and lined by a dielectric layer. At least a portion of the second surface is roughened to form multiple features spaced apart at a distance smaller than a distance between each of the cavities formed in the first surface to enhance extraction of light emitted from the light emitting layer. At least one contact is disposed between the first surface of the semiconductor structure and the substrate.
    Type: Application
    Filed: December 14, 2018
    Publication date: September 12, 2019
    Applicant: Lumileds LLC
    Inventors: Jonathan J. WIERER, Aurelien Jean Francois DAVID, Henry Kwong-Hin CHOY
  • Publication number: 20190103511
    Abstract: A device comprising a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is disclosed. The device comprises a porous region. The device comprises a first layer disposed between the light emitting layer and the porous region. The device comprises a mask layer disposed between the porous region and the first layer. The device comprises a plurality of openings formed in the mask layer.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Applicant: LUMILEDS LLC
    Inventors: Jonathan J. Wierer, John E. Epler
  • Patent number: 10164155
    Abstract: A light emitting device is described. The light emitting device includes a substrate and a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region and has a first surface adjacent the substrate and a second surface opposite the first surface. The first surface of the semiconductor structure multiple cavities formed therein, which extend into at least one of the n-type region and the p-type region. The cavities are spaced apart and lined by a dielectric layer. At least a portion of the second surface is roughened to form multiple features spaced apart at a distance smaller than a distance between each of the cavities formed in the first surface to enhance extraction of light emitted from the light emitting layer. At least one contact is disposed between the first surface of the semiconductor structure and the substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Lumileds LLC
    Inventors: Jonathan J. Wierer, Aurelien Jean Francois David, Henry Kwong-Hin Choy
  • Patent number: 10090435
    Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 2, 2018
    Assignee: LUMILEDS LLC
    Inventors: Jonathan J. Wierer, John E. Epler
  • Publication number: 20180198047
    Abstract: An LED subpixel can be provided with a reflector layer that controls viewing angles. After formation of an array of nanowires including first conductivity type cores and active layers, a second conductivity type semiconductor material layer, a transparent conductive oxide layer, and a dielectric material layer are sequentially formed. An opening is formed through the dielectric material layer over the array of nanowires. The reflector layer can be formed around the array of nanowires and through the opening in the dielectric material layer on the transparent conductive oxide layer. A conductive bonding structure is formed in electrical contact with the reflector layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 12, 2018
    Inventors: Fariba DANESH, Nathan F. GARDNER, Jonathan J. WIERER, JR.
  • Patent number: 9935242
    Abstract: Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 3, 2018
    Assignee: Lumileds LLC
    Inventors: Jonathan J. Wierer, Aurelien Jean Francois David, Henry Kwong-Hin Choy
  • Publication number: 20180053880
    Abstract: A light emitting device is described. The light emitting device includes a substrate and a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region and has a first surface adjacent the substrate and a second surface opposite the first surface. The first surface of the semiconductor structure multiple cavities formed therein, which extend into at least one of the n-type region and the p-type region. The cavities are spaced apart and lined by a dielectric layer. At least a portion of the second surface is roughened to form multiple features spaced apart at a distance smaller than a distance between each of the cavities formed in the first surface to enhance extraction of light emitted from the light emitting layer. At least one contact is disposed between the first surface of the semiconductor structure and the substrate.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Applicant: Lumileds LLC
    Inventors: Jonathan J. WIERER, Aurelien Jean Francois DAVID, Henry Kwong-Hin CHOY
  • Publication number: 20160284935
    Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 29, 2016
    Inventors: Jonathan J. Wierer, John E. Epler
  • Patent number: 9385265
    Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: July 5, 2016
    Assignee: LUMILEDS LLC
    Inventors: Jonathan J. Wierer, Jr., John E. Epler
  • Patent number: 9368677
    Abstract: Selective layer disordering in a doped III-nitride superlattice can be achieved by depositing a dielectric capping layer on a portion of the surface of the superlattice and annealing the superlattice to induce disorder of the layer interfaces under the uncapped portion and suppress disorder of the interfaces under the capped portion. The method can be used to create devices, such as optical waveguides, light-emitting diodes, photodetectors, solar cells, modulators, laser, and amplifiers.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: June 14, 2016
    Assignee: Sandia Corporation
    Inventors: Jonathan J. Wierer, Jr., Andrew A. Allerman
  • Patent number: 9276382
    Abstract: Quantum-size-controlled photoelectrochemical (QSC-PEC) etching provides a new route to the precision fabrication of epitaxial semiconductor nanostructures in the sub-10-nm size regime. For example, quantum dots (QDs) can be QSC-PEC-etched from epitaxial InGaN thin films using narrowband laser photoexcitation, and the QD sizes (and hence bandgaps and photoluminescence wavelengths) are determined by the photoexcitation wavelength.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: March 1, 2016
    Assignee: Sandia Corporation
    Inventors: Arthur J. Fischer, Jeffrey Y. Tsao, Jonathan J. Wierer, Jr., Xiaoyin Xiao, George T. Wang
  • Publication number: 20150364654
    Abstract: Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.
    Type: Application
    Filed: August 27, 2015
    Publication date: December 17, 2015
    Inventors: Jonathan J. WIERER, Aurelien Jean Francois DAVID, Henry Kwong-Hin CHOY
  • Publication number: 20150270136
    Abstract: Quantum-size-controlled photoelectrochemical (QSC-PEC) etching provides a new route to the precision fabrication of epitaxial semiconductor nanostructures in the sub-10-nm size regime. For example, quantum dots (QDs) can be QSC-PEC-etched from epitaxial InGaN thin films using narrowband laser photoexcitation, and the QD sizes (and hence bandgaps and photoluminescence wavelengths) are determined by the photoexcitation wavelength.
    Type: Application
    Filed: February 17, 2015
    Publication date: September 24, 2015
    Inventors: Arthur J. Fischer, Jeffrey Y. Tsao, Jonathan J. Wierer, JR., Xiaoyin Xiao, George T. Wang
  • Patent number: 9142726
    Abstract: Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: September 22, 2015
    Assignee: Philips Lumileds Lighting Company LLC
    Inventors: Aurelien J. F. David, Henry Kwong-Hin Choy, Jonathan J. Wierer, Jr.
  • Patent number: 9000450
    Abstract: A photonic crystal is grown within a semiconductor structure, such as a III-nitride structure, which includes a light emitting region disposed between an n-type region and a p-type region. The photonic crystal may be multiple regions of semiconductor material separated by a material having a different refractive index than the semiconductor material. For example, the photonic crystal may be posts of semiconductor material grown in the structure and separated by air gaps or regions of masking material. Growing the photonic crystal, rather than etching a photonic crystal into an already-grown semiconductor layer, avoids damage caused by etching which may reduce efficiency, and provides uninterrupted, planar surfaces on which to form electric contacts.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Philips Lumileds Lighting Company LLC
    Inventors: Jonathan J. Wierer, Jr., Michael R. Krames, Nathan F. Gardner
  • Publication number: 20150079770
    Abstract: Selective layer disordering in a doped III-nitride superlattice can be achieved by depositing a dielectric capping layer on a portion of the surface of the superlattice and annealing the superlattice to induce disorder of the layer interfaces under the uncapped portion and suppress disorder of the interfaces under the capped portion. The method can be used to create devices, such as optical waveguides, light-emitting diodes, photodetectors, solar cells, modulators, laser, and amplifiers.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 19, 2015
    Inventors: Jonathan J. Wierer, JR., Andrew A. Allerman
  • Patent number: 8895335
    Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: Jonathan J. Wierer, Jr., Andrew A. Allerman