Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: A balanced power amplifier circuit arrangement comprises a driver amplifier stage (22) adapted to receive and amplify a signal. The amplified signal is input to a first coupler (26). The first coupler (26) produces an in-phase signal and an out-of-phase quadrature signal. A first power amplifier (38) receives and amplifies the in-phase signal. A second power amplifier (40) receives and amplifies the out-of-phase signal. A first switch (28) alternately connects an isolated port of the first coupler to ground (32) or a bypass path (36). A second coupler (42) receives and combines the amplified in-phase signal and the amplified out-of-phase signal to produce a combined signal. A second switch (30) alternately connects an isolated port of the second coupler (42) to either ground (34) or the bypass path (36). When the power amplifiers (38, 40) are powered down, the first coupler (26) splits the RF-signal into an in-phase signal and an out-of-phase signal.

Abstract: A battery (102) powers a wireless telephone's power amplifier (106) through a Switch Mode Power Supply (SMPS) (104). The SMPS has a capacity lower than the maximum power requirements of the amplifier. When a controller (116) senses that an amplifier power-requirement threshold has been exceeded, it closes a switch (114) parallel to the SMPS, allowing power to flow from the battery to the amplifier without passing through the SMPS. This architecture allows the use of a smaller SMPS, and eliminates SMPS-generated noise to the amplifier when the amplifier is least able to tolerate such noise, namely, under high power conditions.

Abstract: A balanced power amplifier circuit arrangement comprises a driver amplifier stage (22) adapted to receive and amplify a signal. The amplified signal is input to a first coupler (26). The first coupler (26) produces an in-phase signal and an out-of-phase quadrature signal. A first power amplifier (38) receives and amplifies the in-phase signal. A second power amplifier (40) receives and amplifies the out-of-phase signal. A first switch (28) alternately connects an isolated port of the first coupler to ground (32) or a bypass path (36). A second coupler (42) receives and combines the amplified in-phase signal and the amplified out-of-phase signal to produce a combined signal. A second switch (30) alternately connects an isolated port of the second coupler (42) to either ground (34) or the bypass path (36). When the power amplifiers (38, 40) are powered down, the first coupler (26) splits the RF-signal into an in-phase signal and an out-of-phase signal.

Abstract: Power detectors sense load mismatch conditions and cause the power output of a power amplifier to be reduced in response to a load mismatch. Transmitted and reflected power measurements are used to calculate a load mismatch criterion. A power amplifier is configured based on the calculated load mismatch criterion. A dual-directional coupler may be used to separate a power signal into transmitted and reflected components. With output power reduced under load mismatch conditions, signal distortion levels may be reduced to acceptable levels.

Abstract: A power detector (50) detects a power level of an amplified signal (S20) produced by a power amplifier (16) on the same integrated circuit (100). The power detector compensates for an effect of temperature variations on the magnitude of the detected power level.

Abstract: A power detector (50) detects a power level of an amplified signal (S20) produced by a power amplifier (16) on the same integrated circuit (100). The power detector compensates for an effect of temperature variations on the magnitude of the detected power level.

Abstract: A battery (102) powers a wireless telephone's power amplifier (106) through a Switch Mode Power Supply (SMPS) (104). The SMPS has a capacity lower than the maximum power requirements of the amplifier. When a controller (116) senses that an amplifier power-requirement threshold has been exceeded, it closes a switch (114) parallel to the SMPS, allowing power to flow from the battery to the amplifier without passing through the SMPS. This architecture allows the use of a smaller SMPS, and eliminates SMPS-generated noise to the amplifier when the amplifier is least able to tolerate such noise, namely, under high power conditions.

Abstract: A power amplifier having bias that may be automatically adjusted based on a detected output power level. The amplifier includes one or more amplifier stages operatively coupled to a control unit. The amplifier stage(s) couple together (e.g., in series) and receive and amplify an RF input signal to provide an RF output signal. A power detector detects the RF output signal level (or power) and provides a detected signal. A control unit conditions the detected signal (e.g., with a particular transfer characteristic) to provide at least one conditioned signal. A bias control generator receives the conditioned signal(s) and provides at least one bias control signal, with each bias control signal used to adjust the bias of a respective amplifier stage. The bias adjustment is performed in a manner to achieve the desired level of linearity while minimizing power consumption.