Patents by Inventor Jonathan M. Audy
Jonathan M. Audy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10581330Abstract: A power conversion circuit providing a regulated output voltage to a load can include a switching regulator with an input configured to be coupled to an input voltage source and an output configured to be coupled to the load. The power conversion circuit can further include a metered charge transfer converter, such as a charge pump or a switched or pulsed current source, having an input configured to be coupled to an input voltage source and having an output configured to be coupled to the load. A controller coupled to the metered charge transfer converter can be configured to operate the metered charge transfer converter to deliver energy to the load responsive to a dip of the regulated output voltage below a threshold caused by an increase in current drawn by the load. The metered charge transfer converter may be located closer to the load than the switching regulator.Type: GrantFiled: June 7, 2018Date of Patent: March 3, 2020Assignee: Apple Inc.Inventors: Damon Lee, Jamie L. Langlinais, Jonathan M. Audy, Mark A. Yoshimoto, Rajarshi Paul, Talbott M. Houk
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Publication number: 20190280590Abstract: A power conversion circuit providing a regulated output voltage to a load can include a switching regulator with an input configured to be coupled to an input voltage source and an output configured to be coupled to the load. The power conversion circuit can further include a metered charge transfer converter, such as a charge pump or a switched or pulsed current source, having an input configured to be coupled to an input voltage source and having an output configured to be coupled to the load. A controller coupled to the metered charge transfer converter can be configured to operate the metered charge transfer converter to deliver energy to the load responsive to a dip of the regulated output voltage below a threshold caused by an increase in current drawn by the load. The metered charge transfer converter may be located closer to the load than the switching regulator.Type: ApplicationFiled: June 7, 2018Publication date: September 12, 2019Inventors: Damon Lee, Jamie L. Langlinais, Jonathan M. Audy, Mark A. Yoshimoto, Rajarshi Paul, Talbott M. Houk
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Patent number: 10128755Abstract: A multi-phase switch mode, voltage regulator has a transient mode portion in which a phase control output is coupled to one or more control inputs of one or more switch circuits that conduct inductor current through one or more transient phase inductors, from amongst a number of phase inductors. A slew mode control circuit detects a high slope and then a low slope in the feedback voltage and, in between detection of the high slope and the low slope, pulses the phase control output of the transient mode portion so that the switch circuit that conducts transient phase inductor current adds power to, or sinks power from, the power supply output. Other embodiments are also described.Type: GrantFiled: June 19, 2017Date of Patent: November 13, 2018Assignee: Apple Inc.Inventors: Rajarshi Paul, Parin Patel, Damon Lee, Evaldo Miranda, Jr., Mark A. Yoshimoto, Jamie L. Langlinais, Jonathan M. Audy
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Publication number: 20180013348Abstract: A multi-phase switch mode, voltage regulator has a transient mode portion in which a phase control output is coupled to one or more control inputs of one or more switch circuits that conduct inductor current through one or more transient phase inductors, from amongst a number of phase inductors. A slew mode control circuit detects a high slope and then a low slope in the feedback voltage and, in between detection of the high slope and the low slope, pulses the phase control output of the transient mode portion so that the switch circuit that conducts transient phase inductor current adds power to, or sinks power from, the power supply output. Other embodiments are also described.Type: ApplicationFiled: June 19, 2017Publication date: January 11, 2018Inventors: Rajarshi Paul, Parin Patel, Damon Lee, Evaldo Miranda, JR., Mark A. Yoshimoto, Jamie L. Langlinais, Jonathan M. Audy
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Patent number: 9444333Abstract: In an example, a system and method are disclosed for providing a single control law that is operable to regulate both small-signal, steady-state operation, and large-signal transients of a switching regulator. The control law is based on detecting a zero-crossing of capacitor current, and projecting in advance a turning point for either ramping up or ramping down capacitor voltage at a target voltage. Certain embodiments may realize the control function in high-speed analog components, although certain other embodiments may implement the same or a similar control law in a digital controller.Type: GrantFiled: March 15, 2014Date of Patent: September 13, 2016Assignee: Analog Devices, Inc.Inventors: Jonathan M. Audy, Evaldo M. Miranda
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Publication number: 20140285167Abstract: In an example, a system and method are disclosed for providing a single control law that is operable to regulate both small-signal, steady-state operation, and large-signal transients of a switching regulator. The control law is based on detecting a zero-crossing of capacitor current, and projecting in advance a turning point for either ramping up or ramping down capacitor voltage at a target voltage. Certain embodiments may realize the control function in high-speed analog components, although certain other embodiments may implement the same or a similar control law in a digital controller.Type: ApplicationFiled: March 15, 2014Publication date: September 25, 2014Applicant: ANALOG DEVICES, INC.Inventors: Jonathan M. Audy, Evaldo M. Miranda
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Patent number: 7228373Abstract: A communication system includes a master device which communicates with a chain of serially-connected slave devices. The master originates messages, each of which is intended for a particular ‘target’ slave device. Each message contains a ‘distance to target device’ value equal to the number of devices between the master and target, and a data packet containing data to be conveyed between the master and target. Each slave device determines if the ‘distance to target device’ value indicates that it is the target. If not, the slave device increments or decrements the value in real time, with no latency, and transmits the modified message to the next slave device until received by the target device. In one embodiment, the target device may place data in the data packet, and the slave devices are arranged to buffer the data back to the master device.Type: GrantFiled: March 22, 2005Date of Patent: June 5, 2007Assignee: Analog Devices, Inc.Inventors: Michael P. Daly, Jonathan M. Audy
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Patent number: 7187226Abstract: An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.Type: GrantFiled: January 12, 2005Date of Patent: March 6, 2007Assignee: Analog Devices, Inc.Inventor: Jonathan M. Audy
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Patent number: 6961396Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.Type: GrantFiled: January 26, 2001Date of Patent: November 1, 2005Assignee: Analog Devices, Inc.Inventors: Jonathan M. Audy, Gabor Reizik, Richard Redl, Brian P. Erisman
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Publication number: 20020101945Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Applicant: ANALOG DEVICES, INC.Inventors: Jonathan M. Audy, Richard Redl, Gabor Reizik, Brian P. Erisman
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Patent number: 6229292Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved with a technique referred to as “optimal voltage positioning”, which keeps the output voltage within the specified boundaries while employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed. The invention can be used with regulators subject to design requirements that specify a minimum time Tmin between load transients, and with those for which no Tmin is specified.Type: GrantFiled: April 25, 2000Date of Patent: May 8, 2001Assignee: Analog Devices, Inc.Inventors: Richard Redl, Brian P. Erisman, Jonathan M. Audy, Gabor Reizik
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Patent number: 6204654Abstract: A dynamically boosted current source circuit improves the response speed of a circuit responsive to a transitioning input signal. The circuit's responsiveness varies with the magnitude of the current provided to an identified node, and a current source capable of providing nominal and boosted currents is connected to the node. A threshold detector detects the occurrence of an input signal transition prior to its detection by the responsive circuit, and triggers the current source to provide the boosted current; this improves the responsive circuit's speed by charging or discharging identified node capacitances which hinder its operation. The identified node can be an input node, an output node, or an internal node. The current source provides the boosted current for a predetermined time interval, or until the input signal crosses a second threshold, enabling response speed to be increased without a significant increase in supply current.Type: GrantFiled: January 29, 1999Date of Patent: March 20, 2001Assignee: Analog Devices, Inc.Inventors: Evaldo M. Miranda, Jonathan M. Audy, David Thomson
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Patent number: 6064187Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.Type: GrantFiled: February 12, 1999Date of Patent: May 16, 2000Assignee: Analog Devices, Inc.Inventors: Richard Redl, Brian P. Erisman, Jonathan M. Audy, Gabor Reizik
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Patent number: 5982201Abstract: A low voltage CTAT current source includes a bipolar transistor connected across two series-connected resistors. A voltage developed across the resistors turns on the transistor, making the current through the resistors CTAT. A second transistor supplies the resistor current; its base (if bipolar) is connected to the node between the resistors, which are selected to limit the transistor's base-collector forward bias and collector-emitter voltage to a preselected fraction of the first transistor's V.sub.be, allowing the CTAT current source to operate with supply voltages of less than two junction voltage drops. A PTAT current can be combined with the CTAT current to create a temperature-compensated current. A low voltage current mirror has the respective bases of a pair of cascoded transistors connected across a resistor which is also connected between the bottom transistor's collector and a programming current.Type: GrantFiled: January 13, 1998Date of Patent: November 9, 1999Assignee: Analog Devices, Inc.Inventors: A. Paul Brokaw, Jonathan M. Audy
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Patent number: 5519354Abstract: An IC temperature sensor with a programmable offset generates an output voltage V.sub.o over a desired temperature range that is a PTAT voltage V.sub.PTAT shifted by an offset voltage V.sub.off. A band gap cell generates a basic PTAT voltage across a first resistor to produce a PTAT current I.sub.PTAT. A second resistor is connected from the first resistor to a reference voltage terminal to provide voltage gain. A third resistor is connected across the base-emitter junction of a transistor which is connected from the top of the second resistor to an output terminal at which V.sub.o is generated. The transistor's base-emitter voltage provides a portion of V.sub.off. The third resistor reduces the portion of I.sub.PTAT that flows through the second resistor to provide the remaining portion of V.sub.off. A current source is positioned between the transistor's emitter and the reference voltage terminal to supply its emitter current and the current for the third resistor. The offset voltage V.sub.Type: GrantFiled: June 5, 1995Date of Patent: May 21, 1996Assignee: Analog Devices, Inc.Inventor: Jonathan M. Audy
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Patent number: 5394019Abstract: A resistor ladder (10) includes a plurality of series resistors (16,18,20,22,24,26,28) connected in series with each other between a first terminal (12) and a second terminal (14). A plurality of shunt resistors (60,62,64,66, 68,70) are connected between junctions (48,50,52,54,56) of adjacent series resistors and the second terminal (14). The series resistors (16,18,20,22,24,26,28) and shunt resistors (60,62,64,66,68,70) are formed on a substrate (80) as film resistors which blow open at a predetermined current density. The shunt resistors (60,62,64,66,68,70) have a smaller cross-sectional area than the series resistors (16,18,20,22,24,26,28) such that they successively blow open from the first terminal (12) toward the second terminal (14), while the series resistors (16,18,20,22,24,26,28) do not blow open, as a progressively increasing voltage is applied between the first terminal (12) and the second terminal (14).Type: GrantFiled: August 9, 1993Date of Patent: February 28, 1995Assignee: Analog Devices, Inc.Inventor: Jonathan M. Audy
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Patent number: 5352973Abstract: An output curvature correction is provided for a band-gap reference circuit that exhibits a temperature dependent output error in the form of k.sub.1 T - k.sub.2 Tln(k.sub.3 T) in the absence of the correction. A substantially constant collector current is driven through a correction transistor and used in connection with a proportional to absolute temperature (PTAT) transistor collector current in the uncorrected circuit. The difference between the base-emitter voltages for the two transistors has the form -k.sub.1 'T + k.sub.2 'ln(k.sub.3 'T.sub.). This voltage differential is scaled by an appropriate selection of resistor ratios and combined with the uncorrected circuit output to provide a corrected output that is substantially insensitive to temperature variations.Type: GrantFiled: January 13, 1993Date of Patent: October 4, 1994Assignee: Analog Devices, Inc.Inventor: Jonathan M. Audy
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Patent number: 5291122Abstract: A bandgap voltage reference circuit includes a low temperature coefficient of resistance (TCR) tail resistor connected in series with a high TCR tail resistor, and a low TCR correction resistor connected in parallel with the high TCR resistor. The ratio of resistance values for the parallel resistors is selected to produce a correction voltage that essentially cancels a Tln(T) output deviation from temperature linearity, where T is absolute temperature. Matching voltage-temperature characteristics are obtained by selecting a resistor ratio at which the rate of change in the circuit's output voltage, both with and without the parallel resistors, is substantially zero at approximately the same temperature. While the shape of the compensation voltage-temperature curve is determined by the resistor ratio, it is scaled to the magnitude of the Tln(T) deviation by an appropriate selection of absolute resistor values. The correction resistor is preferably a trimmable thin film element.Type: GrantFiled: June 11, 1992Date of Patent: March 1, 1994Assignee: Analog Devices, Inc.Inventor: Jonathan M. Audy
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Patent number: 5225811Abstract: A temperature limit circuit has a pair of comparators for producing an output signal when a sensed temperature either exceeds of falls below a permissible range. A common impedance circuit uses a single output pin to establish both the upper and lower temperature limits and a hysteresis level at each end of the range. A hysteresis circuit includes two branches, one of which directs a hysteresis current in one direction to a hysteresis resistor at a common input to the comparators to set the hysteresis at one end of the temperature range, and the other of which directs the hysteresis current through the hysteresis resistor in the opposite direction to set the hysteresis at the other end of the temperature range; the oppositely directed current flows establish hysteresis differentials of opposite polarities. A voltage reference circuit that includes a feedback circuit is preferably used for both temperature sensing and to establish a reference current upon which the hysteresis current is based.Type: GrantFiled: February 4, 1992Date of Patent: July 6, 1993Assignee: Analog Devices, Inc.Inventor: Jonathan M. Audy
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Patent number: 5195827Abstract: The temperature at a semiconductor device having a generally non-linear, temperature dependent relationship between a pair of device parameters is determined by applying a plurality of sequential excitations to the device at different excitation levels, sensing the levels of the device parameters that correspond to the sequential excitations, and determining the device temperature from the sequential device parameter levels. The device may include a p-n junction, and is preferably a bipolar transistor whose collector current and base-emitter voltage serve as the parameters from which the temperature is obtained. Using three sequential excitations, an accurate temperature reading can be obtained that substantially cancels the effects of the transistor's parasitic base and emitter resistances. p-n junction diodes and Schottky diodes may also serve as the device, in which case the current through and voltage across the diode are used to determine temperature.Type: GrantFiled: February 4, 1992Date of Patent: March 23, 1993Assignee: Analog Devices, Inc.Inventors: Jonathan M. Audy, Barrie Gilbert