Patents by Inventor Jonathan Yedidia

Jonathan Yedidia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050138516
    Abstract: A method decodes a soft-input cost function for an [N,k]q linear block error- correcting code that has a fast sparse transform factor graph (FSTFG) representation, such as Reed-Solomon codes. First, the code is selected and its FSTFG representation is constructed. The representation is simplified and is made redundant if the improved performance is more important than the increased decoding complexity. An encoding method consistent with the representation is selected. A set of message-update and belief-update rules are selected. The messages are initialized according to a soft-input cost function. An iterative decoding cycle is then begun, in which the first step consists of updating the messages according to the pre-selected message-update rules. In the second step of the decoding cycle, a trial code word is determined from the messages, the pre- selected message-update rules, and the encoding method.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 23, 2005
    Inventor: Jonathan Yedidia
  • Publication number: 20050044475
    Abstract: A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a channel register. An active register represents a current state of the decoder. Each element in the active register can take three states, representing the two possible states of the corresponding bit in the word, and a third state representing uncertainty. Votes from parity checks to elements of the active register are determined from parity checks in the matrix, and the current state of the active register. A recommendation and strength of recommendation for each element in the active register is determined from the votes. The elements in the active register are then updated by comparing the recommendation and strength of recommendation with two thresholds, and the state of the corresponding bit in the received word. When termination conditions are satisfied, the decoder outputs the state of the active register.
    Type: Application
    Filed: August 19, 2003
    Publication date: February 24, 2005
    Inventors: Jonathan Yedidia, Marc Fossorier, Ravi Palanki