Patents by Inventor Jong-Hyuk Kim
Jong-Hyuk Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7719033Abstract: Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.Type: GrantFiled: February 28, 2006Date of Patent: May 18, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hun Jeong, Soon-Moon Jung, Hoon Lim, Won-Seok Cho, Jin-Ho Kim, Chang-Min Hong, Jong-Hyuk Kim, Kun-Ho Kwak
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Patent number: 7709323Abstract: Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line patteType: GrantFiled: May 29, 2009Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Patent number: 7683404Abstract: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.Type: GrantFiled: February 22, 2007Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Hoo-Sung Cho, Jong-Hyuk Kim
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Publication number: 20100012980Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.Type: ApplicationFiled: July 17, 2009Publication date: January 21, 2010Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk Kim, Young-Chul Jang
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Publication number: 20090233405Abstract: Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line patteType: ApplicationFiled: May 29, 2009Publication date: September 17, 2009Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Patent number: 7589375Abstract: A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.Type: GrantFiled: December 20, 2006Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jang, Soon-Moon Jung, Jong-Hyuk Kim, Young-Seop Rah, Han-Byung Park
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Publication number: 20090175746Abstract: A compressor having a casing to which a gas suction pipe is connected; a driving motor provided in the casing; a cylinder; a valve supporting plate (210) covering the cylinder (300), the valve supporting plate (210) having a suction hole (212) for sucking gas into the cylinder (300) and two discharge holes (211) for discharging gas compressed in the cylinder (300); a piston (100) having two protrusions (101) at a pressure surface in correspondence to the two discharge holes (211) of the valve supporting plate (210), the protrusions (101) having different sized cross-sections, the piston being linearly reciprocal in the cylinder (300) by receiving a driving force of the driving motor; a suction valve coupled to the valve supporting plate (210) to open and close the suction hole (212); a discharge valve coupled to the valve supporting plate to open and close the two discharge holes (211).Type: ApplicationFiled: December 29, 2006Publication date: July 9, 2009Inventors: Kyoung-Jun Park, Ji-Young Bae, Jin-Kook Kim, Bum-Joon Kim, Hyuk Nam, Jong-Mok Lee, Jong-Hyuk Kim, Kyeong-Ho Kim
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Patent number: 7554140Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.Type: GrantFiled: January 10, 2007Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Publication number: 20090123305Abstract: A detachable connecting rod includes a first member (410)a large end portion (411) having a trough hole (H1), and a first connection rod portion (412) extending from the large end portion (411), the first connection rod portion (412) having a pair of spaced apart arms defining a coupling groove (413) extending in the same direction as an axial direction of the through hole (H1); a second member (420) including a small end portion having a through hole (H2), and second connection rod portion (422) extending from the small end portion, the second connection rod (422) portion being inserted into the coupling groove (413) and a coupling unit for coupling the first connection rod portion (412) to the second connection rod portion inserted (412) into the coupling groove (413) of the first member (410). The detachable connecting rod is useable in a compressor.Type: ApplicationFiled: December 29, 2006Publication date: May 14, 2009Inventors: Kyoung-Jun Park, Ji-Young Bae, Jin-Kook Kim, Bum-Joon Kim, Hyuk Nam, Jong-Mok Lee, Jong-Hyuk Kim, Kyeong-Ho Kim
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Patent number: 7417286Abstract: Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern.Type: GrantFiled: November 15, 2005Date of Patent: August 26, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Jin Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Jong-Hyuk Kim, Kun-Ho Kwak, Hoon Lim
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Publication number: 20080152866Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20080149021Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Patent number: 7387919Abstract: In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.Type: GrantFiled: November 16, 2005Date of Patent: June 17, 2008Inventors: Kun-Ho Kwak, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Jong-Hyuk Kim
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Patent number: 7358126Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: GrantFiled: January 17, 2006Date of Patent: April 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20080085582Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.Type: ApplicationFiled: January 10, 2007Publication date: April 10, 2008Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Publication number: 20080067573Abstract: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.Type: ApplicationFiled: February 22, 2007Publication date: March 20, 2008Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Hoo-Sung Cho, Jong-Hyuk Kim
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Patent number: 7312110Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.Type: GrantFiled: April 4, 2005Date of Patent: December 25, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kun-Ho Kwak, Sung-Jin Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Hoon Lim, Jong-Hyuk Kim, Myang-Sik Han, Byung-Jun Hwang
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Publication number: 20070241335Abstract: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.Type: ApplicationFiled: June 21, 2007Publication date: October 18, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kun-Ho KWAK, Jae-Hoon JANG, Soon-Moon JUNG, Won-Seok CHO, Hoon LIM, Sung-Jin KIM, Byung-Jun HWANG, Jong-Hyuk KIM
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Patent number: 7276404Abstract: SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.Type: GrantFiled: October 30, 2006Date of Patent: October 2, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Jin Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Kun-Ho Kwak, Jong-Hyuk Kim, Jae-Joo Shim
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Patent number: 7276421Abstract: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer.Type: GrantFiled: August 5, 2005Date of Patent: October 2, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyuk Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Kun-Ho Kwak, Sung-Jin Kim, Jae-Joo Shim