Abstract: A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.

Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.

Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure.

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract: The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.

Abstract: System and method for data mining and feature tracking for fab-wide prediction and control are described. One embodiment is a system comprising a database for storing raw wafer manufacturing data; a data mining module for processing the raw wafer manufacturing data to select the best data therefrom in accordance with at least one of a plurality of knowledge-, statistic-, and effect-based processes; and a feature tracking module associated with the data mining module and comprising a self-learning model wherein a sensitivity of the self-learning model is dynamically tuned to meet real-time production circumstances, the feature tracking module receiving the selected data from the data mining module and generating prediction and control data therefrom; wherein the prediction and control data are used to control future processes in the wafer fabrication facility.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing data sets in a manner so that statistical differences among the manufacturing data sets are reduced. The method includes establishing a database that includes the normalized manufacturing data sets. The method includes normalizing the database in a manner so that the manufacturing data sets in the normalized database are statistically compatible with a selected one of the manufacturing data sets. The method includes predicting performance of a selected one of the semiconductor processes by using the normalized database. The selected semiconductor process corresponds to the selected manufacturing data set. The method includes controlling a semiconductor processing machine in response to the predicted performance.

Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a first plurality of semiconductor wafers; determining a sampling rate to the first plurality of semiconductor wafers based on process quality; determining sampling fields and sampling points to the first plurality of semiconductor wafers; measuring a subset of the first plurality of semiconductor wafers according to the sampling rate, the sampling fields and the sampling points; modifying a second process according to the measuring; and applying the second process to a second plurality of semiconductor wafers.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure.

Abstract: The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Abstract: A method of advanced process control (APC) for semiconductor fabrication is provided. The method includes providing a present wafer to be processed by a semiconductor processing tool, providing first data of previous wafers that have been processed by the semiconductor processing tool, decoupling noise from the first data to generate second data, evaluating an APC performance based on proximity of the second data to a target data, determining a control parameter based on the APC performance, and controlling the semiconductor processing tool with the control parameter to process the present wafer.

Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.

Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.

Abstract: A MIMO optimizer is used to identify tunable process parameters for processing equipment.