Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

Abstract: An image display apparatus and a method of displaying an image are provided. The image display apparatus includes: a display; a graphics processing unit (GPU); and a processor configured to: determine a copy region of a planar-format image based on information regarding a current viewpoint, control the GPU to generate a sphere-format image by mapping an image corresponding to the copy region to a sphere and to generate an output image by rendering the sphere-format image, and control the display to display the output image.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: An image display apparatus and a method of displaying an image are provided. The image display apparatus includes: a display; a graphics processing unit (GPU); and a processor configured to: determine a copy region of a planar-format image based on information regarding a current viewpoint, control the GPU to generate a sphere-format image by mapping an image corresponding to the copy region to a sphere and to generate an output image by rendering the sphere-format image, and control the display to display the output image.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

Abstract: A leakage current compensation device includes a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines, a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells to output a result value based on the sensed amount of leakage current, and a compensation current supply unit configured to receive the result value and supply a compensation current to the operating cell.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.