Patents by Inventor Jong-min Baek
Jong-min Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10008407Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.Type: GrantFiled: December 1, 2015Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Jin Lee, Byung-Hee Kim, Sang-Hoon Ahn, Woo-Kyung You, Jong-Min Baek, Nae-In Lee
-
Patent number: 9991203Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.Type: GrantFiled: October 20, 2016Date of Patent: June 5, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung
-
Patent number: 9984921Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: GrantFiled: November 3, 2017Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
-
Publication number: 20180130697Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.Type: ApplicationFiled: June 7, 2017Publication date: May 10, 2018Inventors: Sang-Shin JANG, Woo-Kyung YOU, Kyu-Hee HAN, Jong-Min BAEK, Viet Ha NGUYEN, Byung-Hee KIM
-
Publication number: 20180124314Abstract: An image display apparatus and a method of displaying an image are provided. The image display apparatus includes: a display; a graphics processing unit (GPU); and a processor configured to: determine a copy region of a planar-format image based on information regarding a current viewpoint, control the GPU to generate a sphere-format image by mapping an image corresponding to the copy region to a sphere and to generate an output image by rendering the sphere-format image, and control the display to display the output image.Type: ApplicationFiled: October 26, 2017Publication date: May 3, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-min BAEK, Young-hyun KIM, Se-hyun KIM, Kwan-sik YANG, Jae-young YOU, Kil-soo CHOI
-
Publication number: 20180102280Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.Type: ApplicationFiled: June 29, 2017Publication date: April 12, 2018Inventors: Viet Ha NGUYEN, Nae In LEE, Thomas OSZINDA, Byung Hee KIM, Jong Min BAEK, Tae Jin YIM
-
Patent number: 9940012Abstract: A display device for displaying an application in an execution area according to a user input is disclosed. The display device includes a user interface configured to receive a user input corresponding to a shape, a display, and a controller configured to determine an application corresponding to the shape and determine an execution area for the application on a screen of the display in response to the user interface receiving the user input, and control the display of the application in the execution area.Type: GrantFiled: August 14, 2014Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kil-soo Choi, Young-il Kim, Jung-rae Kim, Jong-min Baek, Jae-soon Lee
-
Publication number: 20180096880Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.Type: ApplicationFiled: June 2, 2017Publication date: April 5, 2018Inventors: Kyu Hee HAN, Jong Min BAEK, Viet Ha NGUYEN, Woo Kyung YOU, Sang Shin JANG, Byung Hee KIM
-
Patent number: 9929098Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.Type: GrantFiled: February 19, 2016Date of Patent: March 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Jin Yim, Sang-Hoon Ahn, Thomas Oszinda, Jong-Min Baek, Byung Hee Kim, Nae-In Lee, Kee-Young Jun
-
Publication number: 20180076140Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.Type: ApplicationFiled: April 5, 2017Publication date: March 15, 2018Inventors: Byung Hee KIM, Thomas Oszinda, Deok Young Jung, Jong Min Baek, Tae Jin Yim
-
Publication number: 20180053685Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Inventors: Sang Hoon AHN, Jong Min BAEK, Myung Geun SONG, Woo Kyung YOU, Byung Kwon CHO, Byung Hee KIM, Na Ein LEE
-
Publication number: 20180033691Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.Type: ApplicationFiled: December 29, 2016Publication date: February 1, 2018Inventors: Woo Kyung You, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
-
Patent number: 9812450Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.Type: GrantFiled: January 26, 2016Date of Patent: November 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Min Baek, Sang-Hoon Ahn, Woo-Kyung You, Byung-Hee Kim, Young-Ju Park, Nae-in Lee, Kyung-Min Chung
-
Patent number: 9812353Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: GrantFiled: November 17, 2016Date of Patent: November 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
-
Publication number: 20170294337Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Jin-Nam KIM, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
-
Patent number: 9728604Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.Type: GrantFiled: March 3, 2016Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
-
Publication number: 20170213786Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.Type: ApplicationFiled: October 25, 2016Publication date: July 27, 2017Inventors: Sang Hoon AHN, Tae Soo KIM, Jong Min BAEK, Woo Kyung YOU, Thomas OSZINDA, Byung Hee KIM, Nae In LEE
-
Publication number: 20170162431Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: ApplicationFiled: November 17, 2016Publication date: June 8, 2017Inventors: Sang Hoon AHN, Jong Min BAEK, Myung Geun SONG, Woo Kyung YOU, Byung Kwon CHO, Byung Hee KIM, Na Ein LEE
-
Patent number: 9653400Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.Type: GrantFiled: December 30, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jin Yim, Woo-Kyung You, Jong-Min Baek, Sang-Hoon Ahn, Thomas Oszinda, Kee-Young Jun
-
Publication number: 20170133317Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.Type: ApplicationFiled: October 20, 2016Publication date: May 11, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Rak-Hwan KIM, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung