Patents by Inventor Jong Moo Choi

Jong Moo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230033773
    Abstract: An apparatus for storing a key value store file according to an embodiment includes a memory configured to record one or more key values in a predefined unit space based on a data input request from an outside, a controller configured to store data received from the memory in a storage, and the storage configured to include a plurality of zones. The controller is configured to perform a flush operation of storing one or more key values received from the memory as a file in a predefined format in the storage and a compaction operation of merging a plurality of files existing in one level in the storage and recording the merged files as one file in another level.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 2, 2023
    Inventors: Jong Moo CHOI, Myung Hoon OH
  • Patent number: 11373892
    Abstract: A method for preventing a collision in a wafer processing system is provided. The method includes aligning a first sensor and a second sensor. The first sensor is disposed on a predetermined position of an elevating member connected to a bottom of a vertical wafer boat of the wafer processing system, and the second sensor is disposed on a shutter of a chamber of the wafer processing system. The method further includes activating the first sensor and the second sensor to monitor a path alongside the vertical wafer boat when the chamber is closed by the shutter.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 28, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Sung-Ki Kim, Jong-Moo Choi, Chiku Choi, Eun-Joung Lee
  • Patent number: 11340530
    Abstract: The instant disclosure includes an implanting apparatus and a method thereof. The implanting apparatus has a chuck configured to carry a substrate is rotated a number of times at an angle during ion implantation. In this way, masks used during semiconductor fabrication is reduced.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 24, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Jong-Moo Choi, Sung-Ki Kim
  • Patent number: 11170975
    Abstract: A collecting plate is disclosed. The collecting plate includes a body having a plurality of holes arranged in an array and a plurality of mitt members respectively disposed over the plurality of holes. The holes and the mitt members are configured to capture and store contaminant particle and prevent contaminant particles from entering processing chamber.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 9, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Heung-Woo Park, Hasung Lee, Jong-Moo Choi, Sung-Ki Kim
  • Publication number: 20210143042
    Abstract: A method for preventing a collision in a wafer processing system is provided. The method includes aligning a first sensor and a second sensor. The first sensor is disposed on a predetermined position of an elevating member connected to a bottom of a vertical wafer boat of the wafer processing system, and the second sensor is disposed on a shutter of a chamber of the wafer processing system. The method further includes activating the first sensor and the second sensor to monitor a path alongside the vertical wafer boat when the chamber is closed by the shutter.
    Type: Application
    Filed: February 11, 2020
    Publication date: May 13, 2021
    Inventors: SUNG-KI KIM, JONG-MOO CHOI, CHIKU CHOI, EUN-JOUNG LEE
  • Patent number: 10923311
    Abstract: An apparatus for ion implantation is disclosed. The apparatus comprising an arc chamber and an electron source device. The electron source device includes a cathode and a filament. The filament is disposed within the cathode. The cathode has a body and a cap disposed over the body. The cap has a receiving surface and a emitting surface opposite the receiving surface. The emitting surface has a convex shape facing the receiving area of the arc chamber and the receiving surface has a conical shape where a center area is a flat surface and the center area being surrounded by a tapered sidewall.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 16, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Keewoung Choi, Jong-Moo Choi, Heung-Woo Park, Hasung Lee
  • Publication number: 20200218156
    Abstract: The instant disclosure includes an implanting apparatus and a method thereof. The implanting apparatus has a chuck configured to carry a substrate is rotated a number of times at an angle during ion implantation. In this way, masks used during semiconductor fabrication is reduced.
    Type: Application
    Filed: November 11, 2019
    Publication date: July 9, 2020
    Inventors: JONG-MOO CHOI, SUNG-KI KIM
  • Publication number: 20200216946
    Abstract: A collecting plate is disclosed. The collecting plate includes a body having a plurality of holes arranged in an array and a plurality of mitt members respectively disposed over the plurality of holes. The holes and the mitt members are configured to capture and store contaminant particle and prevent contaminant particles from entering processing chamber.
    Type: Application
    Filed: November 11, 2019
    Publication date: July 9, 2020
    Inventors: HEUNG-WOO PARK, HASUNG LEE, JONG-MOO CHOI, SUNG-KI KIM
  • Publication number: 20200219761
    Abstract: A method of forming an oxide structure is disclosed. The method includes forming trenches on a top surface of a substrate and performing a surface treatment process on the substrate. The surface treatment includes forming an amorphous layer on the substrate, removing a portion of the amorphous layer to form a liner layer, and forming a dielectric liner on the liner layer. The liner layer formed are substantially uniform in thickness to prevent contamination and pinhole defects on the oxide structure.
    Type: Application
    Filed: November 11, 2019
    Publication date: July 9, 2020
    Inventors: JONG-MOO CHOI, HEUNG-WOO PARK, SUNG-KI KIM
  • Patent number: 9646985
    Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 9, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yoo Hyun Noh, Jong Moo Choi, Young Soo Ahn
  • Patent number: 9513821
    Abstract: The present invention relates to an apparatus and method for indicating flash memory life. While data is being stored in a flash memory, the number of writes in a plurality of blocks of the flash memory increases. The amount of flash memory life is calculated on the basis of the number of write times in the plurality of blocks. The calculated amount of life can be transmitted to a host. In addition, when the calculated amount of life is greater than a threshold value, a signal providing notice that the life of the flash memory has reached a dangerous level can be output.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: December 6, 2016
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jae Hyuk Cha, Soo Yong Kang, You Jip Won, Tae Hwa Lee, Ho Young Jung, Sung Roh Yoon, Jong Moo Choi
  • Patent number: 9501239
    Abstract: The present invention relates to a grouping method and device for enhancing redundancy removing performance for a storage unit such as a hard disk, a solid state disk (SSD), etc. The grouping method for enhancing performance of a redundancy removing technology may include: extracting samples from data that is stored in a buffer of a memory and is standing by to be processed; performing remaining calculations on the extracted samples; and grouping samples by connecting them to a bucket corresponding to a resultant value of the remaining calculations.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 22, 2016
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Jong Moo Choi, Sung Roh Yoon, Jong Hwa Kim, Ik Joon Son, Sang Yup Lee
  • Patent number: 9496051
    Abstract: Provided is a control device for managing a plurality of memory channels driven through multichannel interleaving. The apparatus includes a stripe configuring unit for configuring a stripe according to a physical number of pages included in the plurality of memory channels, and a parity generating unit for generating parity data on the configured stripe.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: November 15, 2016
    Assignee: TLI INC.
    Inventors: Jae Ho Kim, Jong Min Lee, Jong Moo Choi, Dong Hee Lee, Sam Hyuk Noh
  • Patent number: 9298384
    Abstract: The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit. Additionally, the storage device divides a logical address space into at least one area, and maps an address using the minimum units of different mappings in each divided area.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 29, 2016
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Sung Min Park, Sung Roh Yoon, Jong Moo Choi
  • Patent number: 9298578
    Abstract: The present invention relates to a storage device that uses a flash memory that performs power loss recovery, and to a method of power loss recovery by using the storage device using the flash memory. The storage device stores change information on metadata in physical pages in which one or more logical pages are compressed and stored. The change information on the metadata is information representing how the metadata is changed in association with data in the one or more logical pages. The storage device may synchronize the metadata in the flash memory and recover the metadata by applying the change information on the metadata to the synchronized metadata when a power supply is disrupted.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 29, 2016
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Dong Wook Kim, Sung Roh Yoon, Jong Moo Choi
  • Patent number: 9293360
    Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jung Il Cho, Jong Moo Choi, Eun Joo Jung
  • Publication number: 20150006794
    Abstract: The present invention relates to an apparatus and method for controlling multi-way NAND flashes using input-output pins. The apparatus for controlling multi-way NAND flashes includes: a NAND flash monitor for confirming each state of a plurality of NAND flashes by using a read status command which checks whether an inner operation of the NAND flash is performed normally; and a scheduler for determining the order in which each of the NAND flashes occupies an input-output bus.
    Type: Application
    Filed: December 10, 2012
    Publication date: January 1, 2015
    Applicant: Industry-University Cooperation Foundation Hanyang University
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Sung Roh Yoon, Myung Hyun Rhee, Jong Moo Choi
  • Publication number: 20140380092
    Abstract: Provided is a control device for managing a plurality of memory channels driven through multichannel interleaving. The apparatus includes a stripe configuring unit for configuring a stripe according to a physical number of pages included in the plurality of memory channels, and a parity generating unit for generating parity data on the configured stripe.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 25, 2014
    Inventors: Jae Ho Kim, Jong Min Lee, Jong Moo Choi, Dong Hee Lee, Sam Hyuk Noh
  • Patent number: RE45577
    Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: June 23, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-soo Kim, Gui-Yong Lee, Jong-Min Kim, Ji-hyun In, Je-sung Kim, Sam-hyuk Noh, Sang-lyul Min, Dong-hee Lee, Jae-yong Jeong, Yoo-kun Cho, Jong-moo Choi
  • Patent number: RE46404
    Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bum-Soo Kim, Gui-Young Lee, Jong-Min Kim, Ji-Hyun In, Je-Sung Kim, Sam-Hyuk Noh, Sang-Lyul Min, Dong-Hee Lee, Jae-Yong Jeong, Yoo-Kun Cho, Jong-Moo Choi