Abstract: The present invention relates to an apparatus for security enhancement in closed circuit television (CCTV) using hardware security module and the method by using the same, in which the apparatus is configured to encrypt video data in the process of encoding raw images photographed from IP (Internet Protocol) camera or packetizing the encoded images by using HSM (Hardware Security Moule) embedded in the IP camera, to enable a user to play the encrypted video data after decrypting the encrypted video data by using encryption key which is periodically created and discarded, and not to provide the video data to unauthenticated decvices by constructing secure communication channels among IP camera, user terminal and NVR based on authentication key. Thus, the apparatus prevents the video data from being leaked into network as the video data are non-encrypted and makes it impossible to decrypt the encrypted video data even if the encrypted video data are leaked into network.

Abstract: Disclosed are a real time remote monitoring system and a method therefore using an ADSL in a reverse direction. The real time remote monitoring system performs a remote monitoring in real time by compression-encoding a plurality of monitored image data or audio data in a bit stream, generating a motion detection signal for each image data, and by compressing/transmitting video or video/audio data with an ADSL modem installed in a reverse direction.

Abstract: Disclosed are a real time remote monitoring system and a method therefore using an ADSL in a reverse direction.

Abstract: A data transmission circuit includes a cyclic check (CRC) circuit which improves operation speed of the overall system by checking errors for safe data transmission and a data rate control circuit of which the rate control portion required for data interface includes two simple counter logics to control the data rate during data interface.

Abstract: A method selects a requantization step size which abruptly changes a bit-rate in a piecewise linearly decreasing model and controls the bit-rate.

Abstract: A dematrixing processor for an MPEG-2 multichannel audio decoder, which is capable of performing a decoding matrix process with respect to five compositely decoded signals to restore them to their original status. To this end, the dematrixing processor comprises an arithmetic/control logic unit for performing a dematrixing operation with respect to the five compositely decoded signals to restore them to their original status, and an IIR filter for low pass filtering an output signal from the arithmetic/control logic unit and providing the low pass filtered result to the arithmetic/control logic unit.

Abstract: A synthesis filter for an MPEG-2 audio decoder comprising a first coefficient ROM for storing cosine matrix coefficients therein, a first queue memory for storing subband data therein, a first MAC unit for performing a matrixing operation by multiplying the subband data stored in the first queue memory by the cosine matrix coefficients stored in the first coefficient ROM, a second queue memory for storing output data from the first MAC unit therein, a third queue memory being copied with the contents of the second queue memory, a second coefficient ROM for storing window coefficients therein, a second MAC unit for synthesizing the contents copied to the third queue memory with the window coefficients stored in the second coefficient ROM to produce audio data, an FIFO memory for storing the audio data from the second MAC unit therein, a D/A converter for converting the audio data stored in the FIFO memory into an analog audio signal and outputting the converted analog audio signal to a speaker, and a controlle

Abstract: A composite decoding device for an MPEG-2 multichannel audio decoder. The composite decoding device is capable of simultaneously decoding information coded in a dynamic crosstalk coding manner and information coded in a phantom coding manner. To this end, the composite decoding device comprises an arithmetic unit for receiving a control word, information and a scale factor from a first-in-first-out memory, performing an arithmetic operation with respect to the received information and scale factor on the basis of a dynamic crosstalk coding manner or a phantom coding manner determined by the received control word and outputting the arithmetic result to a dual port memory, and a controller for generating a plurality of sequential control signals in response to the control word from the first-in-first-out memory to control the arithmetic unit.