Patents by Inventor Jong-yeul Jeong

Jong-yeul Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10700265
    Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 30, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Francois Hebert, Seong Woo Lee, Jong Yeul Jeong, Hee Baeg An, Kang Sup Shin, Seong Min Choe, Young Joon Kim
  • Patent number: 10636703
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: April 28, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jong-yeul Jeong
  • Patent number: 10256396
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: April 9, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
  • Publication number: 20180240965
    Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 23, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Francois HEBERT, Seong Woo LEE, Jong Yeul JEONG, Hee Baeg AN, Kang Sup SHIN, Seong Min CHOE, Young Joon KIM
  • Patent number: 10003013
    Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing are comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 19, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, Seong Woo Lee, Jong Yeul Jeong, Hee Baeg An, Kang Sup Shin, Seong Min Choe, Young Joon Kim
  • Patent number: 9558992
    Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 31, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Tae Jong Lee, Kang Sup Shin, Si Bum Kim, Yang Beom Kang, Jong Yeul Jeong
  • Publication number: 20160322561
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Kwan Soo KIM, Dong Joon KIM, Seung Han RYU, Hee Baeg AN, Jong Yeul JEONG, Kyung Soo KIM, Kang Sup SHIN
  • Publication number: 20160260634
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Application
    Filed: May 12, 2016
    Publication date: September 8, 2016
    Applicant: Magnachip Semiconductor, Ltd.
    Inventor: Jong-yeul JEONG
  • Patent number: 9419206
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: August 16, 2016
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
  • Publication number: 20160225661
    Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.
    Type: Application
    Filed: April 5, 2016
    Publication date: August 4, 2016
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Kwan Soo KIM, Tae Jong LEE, Kang Sup SHIN, Si Bum KIM, Yang Beom KANG, Jong Yeul JEONG
  • Patent number: 9373591
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 21, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jong-yeul Jeong
  • Patent number: 9362207
    Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 7, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kwan-soo Kim, Tae-jong Lee, Kang-sup Shin, Si-bum Kim, Yang-beom Kang, Jong-yeul Jeong
  • Publication number: 20150255709
    Abstract: Provided is a magnetic field sensing device (or Hall device) including a magnetic sensor (or Hall sensor) that is provided in buried form inside of a semiconductor substrate. A top portion of the magnetic field sensing device is connected to analog and digital circuitry, and the magnetic sensor included in the magnetic field sensing device obtains magnetic data that is provided to the circuitry. Accordingly, a magnetic field sensor having a reduced size is produced.
    Type: Application
    Filed: August 28, 2014
    Publication date: September 10, 2015
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Francois HEBERT, Seong Woo LEE, Jong Yeul JEONG, Hee Baeg AN, Kang Sup SHIN, Seong Min CHOE, Young Joon KIM
  • Patent number: 9018028
    Abstract: A magnetic sensor and a manufacturing method thereof are provided. The magnetic sensor includes: a substrate comprising a plurality of Hall elements, a protective layer formed on the substrate, a base layer formed on the protective layer, and an integrated magnetic concentrator (IMC) formed on the base layer and comprising a surface with an elevated portion. The base layer has a larger cross-sectional area than the IMC.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 28, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Seung Han Ryu, Jong Yeul Jeong, Kwan Soo Kim
  • Publication number: 20140367813
    Abstract: A magnetic sensor and a manufacturing method thereof are provided. The magnetic sensor includes: a substrate comprising a plurality of Hall elements, a protective layer formed on the substrate, a base layer formed on the protective layer, and an integrated magnetic concentrator (IMC) formed on the base layer and comprising a surface with an elevated portion. The base layer has a larger cross-sectional area than the IMC.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 18, 2014
    Applicant: MagnaChip Seminconductor, Ltd.
    Inventors: Seung Han RYU, Jong Yeul JEONG, Kwan Soo KIM
  • Publication number: 20140252514
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Application
    Filed: July 25, 2013
    Publication date: September 11, 2014
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo KIM, Dong Joon KIM, Seung Han RYU, Hee Baeg AN, Jong Yeul JEONG, Kyung Soo KIM, Kang Sup SHIN
  • Publication number: 20140035146
    Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.
    Type: Application
    Filed: December 14, 2012
    Publication date: February 6, 2014
    Inventors: Kwan-soo Kim, Tae-jong Lee, Kang-sup Shin, Si-bum Kim, Yang-beom Kang, Jong-yeul Jeong
  • Publication number: 20110272818
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Application
    Filed: November 2, 2010
    Publication date: November 10, 2011
    Inventor: Jong-yeul Jeong