Patents by Inventor Joo Hwan Cho
Joo Hwan Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940837Abstract: A display that includes a display panel and a window laminated with the display panel is presented. The display panel may include: a main panel region including a first side extending in a first direction and a second side extending in a second direction crossing the first direction; a first sub-panel region that is in contact with the first side and is bent; and a second sub-panel region that is in contact with the second side and is bent. A panel corner part of the main panel region adjacent to the first sub-panel region and the second sub-panel region is rounded.Type: GrantFiled: May 29, 2019Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Seung-Hwan Cho, Jong Hyun Choi, Ju Chan Park, Joo Sun Yoon, Jong Hyuk Lee
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Patent number: 11926310Abstract: Controlling a speed limit includes determining a virtual vehicle speed as being a lower one of a vehicle speed and a target limit speed, determining a virtual APS value as being a larger one of a first APS value and a second APS value, transitioning to a second mode at a point in time at which an actual APS value and the second APS value become different, when it is expected to transition to the second mode, among a first mode for sustaining a SOC of a battery at the target limit speed and the second mode for depleting the SOC, and determining a transmission gear position by applying the determined virtual vehicle speed and the determined virtual APS value to one of a first shifting pattern and a second shifting pattern.Type: GrantFiled: September 28, 2020Date of Patent: March 12, 2024Assignees: Hyundai Motor Company, Kia Motors CorporationInventors: Hui Un Son, Sang Joon Kim, Kyu Hwan Jo, Sung Bae Jeon, Sung Hoon Yu, Joo Young Kim, Jin Kyeom Cho
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Publication number: 20240067079Abstract: A brake lamp control method of a vehicle is provided. The method includes determining whether a deceleration of the vehicle based on regenerative brake through the electric motor is present in a hysteresis period between an off threshold as a reference for turning off a brake lamp and an on threshold as a reference for turning on the brake lamp. When the deceleration of the vehicle is present in the hysteresis period, the method includes determining a state of the brake lamp before the deceleration of the vehicle enters the hysteresis period. In response to determining that the brake lamp is turned on or off for a reason except for the regenerative brake before the deceleration of the vehicle enters the hysteresis period, a request for turning on the brake lamp is set or reset based on the regenerative brake in response to the determined state of the brake lamp.Type: ApplicationFiled: November 2, 2023Publication date: February 29, 2024Inventors: Hui Un Son, Sang Joon Kim, Kyu Hwan Jo, Sung Bae Jeon, Sung Hoon Yu, Joo Young Kim, Jin Kyeom Cho
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Publication number: 20240069524Abstract: Disclosed is an apparatus for excitation signal generation for a resolver. The apparatus includes a sine wave generator that generates a sine wave based on a square wave, an amplifier that amplifies the sine wave, a differential signal generator that converts, into a differential signal, the amplified sine wave, a driver that inputs the differential signal to a coil, and a processor that generates an excitation signal by increasing a voltage of the sine wave from a start voltage to a target voltage through at least one of the sine wave generator and the amplifier based on a transient current that flows into the coil in a transient response interval.Type: ApplicationFiled: December 27, 2022Publication date: February 29, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Yun Ho CHOI, Hyung Min PARK, Joo Won PARK, Yeon Ho KIM, Won Hee JO, Tae Hwan KANG, Beom Cheol CHO
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Patent number: 10734951Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.Type: GrantFiled: April 4, 2018Date of Patent: August 4, 2020Assignees: SK hynix Inc., NORTHEASTERN UNIVERSITYInventors: Hae Kang Jung, Yong Suk Choi, Yong Bin Kim, Gyunam Jeon, Dae-Han Kwon, Joo Hwan Cho
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Publication number: 20190312550Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: Hae Kang JUNG, Yong Suk CHOI, Yong Bin KIM, Gyunam JEON, Dae-Han KWON, Joo Hwan CHO
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Patent number: 9496878Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.Type: GrantFiled: December 13, 2012Date of Patent: November 15, 2016Assignee: SK Hynix Inc.Inventors: Hae-Rang Choi, Joo-Hwan Cho, Kwang-Jin Na, Kwan-Dong Kim
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Patent number: 9019784Abstract: A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.Type: GrantFiled: December 9, 2013Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventors: Sang Il Park, Joo Hwan Cho
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Publication number: 20150071014Abstract: A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.Type: ApplicationFiled: December 9, 2013Publication date: March 12, 2015Applicant: SK hynix Inc.Inventors: Sang Il PARK, Joo Hwan CHO
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Publication number: 20140049310Abstract: A semiconductor device includes a plurality of oscillation signal generation units configured to output a plurality of oscillation signals whose cycles are adjusted according to a PN ratio, which is a size ratio of a PMOS transistor to an NMOS transistor, and a selection unit configured to selectively output the oscillation signals outputted from the plurality of oscillation signal generation units in response to a test mode signal.Type: ApplicationFiled: December 10, 2012Publication date: February 20, 2014Applicant: SK HYNIX INC.Inventors: Yong-Suk JOO, Joo-Hwan CHO
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Publication number: 20130294186Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.Type: ApplicationFiled: December 13, 2012Publication date: November 7, 2013Applicant: SK HYNIX INC.Inventors: Hae-Rang CHOI, Joo-Hwan CHO, Kwang-Jin NA, Kwan-Dong KIM
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Patent number: 7859319Abstract: A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.Type: GrantFiled: December 24, 2007Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventor: Joo Hwan Cho
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Patent number: 7859939Abstract: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.Type: GrantFiled: December 3, 2008Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong-Suk Joo, Joo-Hwan Cho
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Publication number: 20100008177Abstract: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.Type: ApplicationFiled: December 3, 2008Publication date: January 14, 2010Inventors: Yong-Suk Joo, Joo-Hwan Cho
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Publication number: 20090033396Abstract: A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.Type: ApplicationFiled: December 24, 2007Publication date: February 5, 2009Inventor: Joo Hwan CHO
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Patent number: 6990033Abstract: Disclosed is a buffer device for a clock enable signal in a memory device that is used when the memory device escapes from a self-refresh mode. The buffer device includes a first buffer for comparing a clock enable signal with an external reference voltage in accordance with a self-refresh flag signal, a second buffer for outputting a signal corresponding to the self-refresh flag signal as the clock enable signal, a comparator for comparing the external reference voltage applied from an outside with an internal reference voltage internally generated, and a switching unit for selecting and outputting an output of the first buffer if the external reference voltage is higher than the internal reference voltage and selecting and outputting an output of the second buffer if the external reference voltage is lower than the internal reference voltage in accordance with an output signal of the comparator.Type: GrantFiled: October 12, 2004Date of Patent: January 24, 2006Assignee: Hynix Semiconductor Inc.Inventor: Joo Hwan Cho
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Patent number: 6034898Abstract: A DRAM for increasing a data output driver current shares pull-up transistors and pull-down transistors of the unused 8 data output buffers with other pull-up transistors and other pull-down transistors of the used 8 data output buffers, for example 8 pins are used in a product having 16 data pins, thereby increasing a data output driver current.Type: GrantFiled: June 19, 1998Date of Patent: March 7, 2000Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Joo Hwan Cho