Abstract: An anode active material for a lithium secondary battery and a lithium secondary battery including the same are provided. The anode active material includes a plurality of composite particles, each composite particle including a silicon-based active material particle including silicon; and a carbon coating layer formed on at least a portion of a surface of the silicon-based active material particle, wherein a relative standard deviation of G/Si peak intensity ratios of a Raman spectrum as defined in Equation 1 measured for each of 50 different composite particles among the plurality of composite particles is 50% or less.

Abstract: An anode active material for a secondary battery according to an embodiment of the present application includes lithium-silicon composite oxide particle. The lithium-silicon composite oxide particles include at least one selected from the group consisting of Li2SiO3 and Li2Si2O5 and have a phase fraction ratio defined by Equation 1 of 1.0 or less. A content of particles having a diameter of less than 3 ?m is 5 vol % or less based on a total volume of the lithium-silicon composite oxide particles.

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

Abstract: A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

Abstract: A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.