Patents by Inventor Joon-Sung Lim

Joon-Sung Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10886296
    Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungjoong Kim, Joon-Sung Lim, Sung-Min Hwang
  • Publication number: 20200403263
    Abstract: The present invention is a method for manufacturing a secondary battery. An electrode assembly and an electrolyte are accommodated into a body of a battery case. The body of the battery case has an accommodation part and a gas pocket part, and a passage that extends from the accommodation part to the outside discharges an internal gas from the accommodation part through the gas pocket part. The battery case is seated in a seating step on a support block, which has an inclined part on a side surface thereof, to support the battery case. The body is pressed to discharge a gas accommodated in the accommodation part through the gas pocket part in the battery case. This method allows easy discharging of internal gas while reducing discharge of the electrolyte with the gas.
    Type: Application
    Filed: December 7, 2018
    Publication date: December 24, 2020
    Applicant: LG CHEM, LTD.
    Inventors: Dong Hun BAE, Hyo Jin PARK, Suk Hyun HONG, Joon Sung BAE, Beom Koon LEE, Dae Bong LIM, Jin Woo HEO
  • Publication number: 20200373324
    Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.
    Type: Application
    Filed: January 27, 2020
    Publication date: November 26, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: BYUNGJIN LEE, Dong-sik Lee, Joon-Sung Lim
  • Patent number: 10840256
    Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Zhiliang Xia, Ahn-Sik Moon, Se-Jun Park, Joon-Sung Lim, Sung-Min Hwang
  • Patent number: 10840187
    Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-woo Kim, Joon-sung Lim, Jang-gn Yun, Sung-min Hwang
  • Patent number: 10796991
    Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-Gn Yun, Jaesun Yun, Joon-Sung Lim
  • Patent number: 10797068
    Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Sung Lim, Jang-Gn Yun, Jaesun Yun
  • Publication number: 20200311667
    Abstract: An operating method of a manufacturing service device for managing a floating factory including obtaining demand information on an electronic product at a demand location, calculating cost information of at least one floating factory of a plurality of floating factories based on the demand information and status information of each of the floating factories, selecting a floating factory from the plurality of floating factories corresponding to the calculated cost information indicating a lowest cost, generating movement scheduling information of the selected floating factory based on the demand location and manufacturing locations of components of the electronic product, transmitting the movement scheduling information to the selected floating factory, configuring the selected floating factory to manufacture the electronic product and test the electronic product for defects based on the movement scheduling information, while moving to the demand location may be provided, and supplying the electronic product t
    Type: Application
    Filed: February 5, 2020
    Publication date: October 1, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Joon-Sung LIM
  • Publication number: 20200303284
    Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.
    Type: Application
    Filed: December 20, 2019
    Publication date: September 24, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Woo-Sung YANG, Joon-Sung LIM, Sung-Min HWANG, Ji-Young KIM, Ji-Won KIM
  • Publication number: 20200295042
    Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Inventors: Joon-Sung LIM, Jang-Gn YUN, Jaesun YUN
  • Publication number: 20200176464
    Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.
    Type: Application
    Filed: July 16, 2019
    Publication date: June 4, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong Hoon Jang, Woo Sung YANG, Joon Sung LIM, Sung Min HWANG
  • Publication number: 20200091084
    Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Inventors: Young-woo KIM, Joon-sung LIM, Jang-gn YUN, Sung-min HWANG
  • Patent number: 10593689
    Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Song, Jae-Hwang Sim, Joon-Sung Lim
  • Publication number: 20200031879
    Abstract: The present invention relates to a composition for preventing, improving, or treating aging, wherein the composition comprises a recombinant protein of flagellin, which is the constituent of Vibrio vulnificus flagella, fused with a pathogenic protein antigen, as an active component. According to the present invention, the recombinant protein of the present invention can improve external and internal aging-related malfunctions and enhance immunity. Also, the composition of the present invention can easily perform immunization through mucosal administration.
    Type: Application
    Filed: July 29, 2019
    Publication date: January 30, 2020
    Inventors: Kyung A. CHO, Jae Sung LIM, Joon Haeng RHEE
  • Publication number: 20190393243
    Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungjoong KIM, Joon-Sung LIM, Sung-Min HWANG
  • Patent number: 10504844
    Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-woo Kim, Joon-sung Lim, Jang-gn Yun, Sung-min Hwang
  • Publication number: 20190312054
    Abstract: A three-dimensional semiconductor device and method of fabrication is provided. The three-dimensional semiconductor device includes a stacked structure on a lower structure. The stacked structure includes interlayer insulating layers and gate electrodes. The device also includes a channel structure on the lower structure, with the channel structure including a horizontal portion between the stacked structure and the lower structure. The channel structure also includes a plurality of vertical portions extended in a vertical direction. The device also includes support patterns on the lower structure. In addition, the device includes a gate dielectric structure having a lower portion and upper portions. The method of fabrication includes forming the stacked structure with holes. The method also includes removing a sacrificial layer from a horizontal area above the lower structure and forming a channel structure within the holes and within a horizontal space made by removal of the sacrificial layer.
    Type: Application
    Filed: January 3, 2019
    Publication date: October 10, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang Gn YUN, Joon Sung Lim, Eun Suk Cho
  • Patent number: 10407471
    Abstract: The present invention relates to a composition for preventing, improving, or treating aging, wherein the composition comprises a recombinant protein of flagellin, which is the constituent of Vibrio vulnificus flagella, fused with a pathogenic protein antigen, as an active component. According to the present invention, the recombinant protein of the present invention can improve external and internal aging-related malfunctions and enhance immunity. Also, the composition of the present invention can easily perform immunization through mucosal administration.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 10, 2019
    Assignee: INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITY
    Inventors: Kyung A. Cho, Jae Sung Lim, Joon Haeng Rhee
  • Patent number: 10411032
    Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungjoong Kim, Joon-Sung Lim, Sung-Min Hwang
  • Publication number: 20190198511
    Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn YUN, Zhiliang XIA, Ahn-Sik MOON, Se-Jun PARK, Joon-Sung LIM, Sung-Min HWANG