Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

Abstract: A three-dimensional semiconductor memory device and an electronic system including the same are discussed. The device may include: a stack structure including electrode layers and inter-electrode insulating layers that are alternately stacked on a substrate; one or more vertical semiconductor structures that extend into the stack structure and are adjacent to the substrate; one or more vertical conductive structures arranged in a first direction between adjacent ones of the one or more vertical semiconductor structures and extending into the stack structure and are adjacent to the substrate; and a conductive line portion on the stack structure that extends in the first direction to connect the one or more vertical conductive structures to each other. The conductive line portion and the vertical conductive structures may be connected to form a single unit.

Abstract: An operating method of a manufacturing service device for managing a floating factory including obtaining demand information on an electronic product at a demand location, calculating cost information of at least one floating factory of a plurality of floating factories based on the demand information and status information of each of the floating factories, selecting a floating factory from the plurality of floating factories corresponding to the calculated cost information indicating a lowest cost, generating movement scheduling information of the selected floating factory based on the demand location and manufacturing locations of components of the electronic product, transmitting the movement scheduling information to the selected floating factory, configuring the selected floating factory to manufacture the electronic product and test the electronic product for defects based on the movement scheduling information, while moving to the demand location may be provided, and supplying the electronic product t

Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.

Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate, The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.