Patents by Inventor Joon-Sung Lim
Joon-Sung Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10796991Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.Type: GrantFiled: October 4, 2018Date of Patent: October 6, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Gn Yun, Jaesun Yun, Joon-Sung Lim
-
Patent number: 10797068Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.Type: GrantFiled: July 27, 2018Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Sung Lim, Jang-Gn Yun, Jaesun Yun
-
Publication number: 20200311667Abstract: An operating method of a manufacturing service device for managing a floating factory including obtaining demand information on an electronic product at a demand location, calculating cost information of at least one floating factory of a plurality of floating factories based on the demand information and status information of each of the floating factories, selecting a floating factory from the plurality of floating factories corresponding to the calculated cost information indicating a lowest cost, generating movement scheduling information of the selected floating factory based on the demand location and manufacturing locations of components of the electronic product, transmitting the movement scheduling information to the selected floating factory, configuring the selected floating factory to manufacture the electronic product and test the electronic product for defects based on the movement scheduling information, while moving to the demand location may be provided, and supplying the electronic product tType: ApplicationFiled: February 5, 2020Publication date: October 1, 2020Applicant: Samsung Electronics Co., Ltd.Inventor: Joon-Sung LIM
-
Publication number: 20200312862Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Min HWANG, Joon-Sung LIM, Eunsuk CHO
-
Publication number: 20200312877Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Min HWANG, Joon-Sung LIM, Jihye KIM
-
Publication number: 20200303284Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.Type: ApplicationFiled: December 20, 2019Publication date: September 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Woo-Sung YANG, Joon-Sung LIM, Sung-Min HWANG, Ji-Young KIM, Ji-Won KIM
-
Publication number: 20200295042Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.Type: ApplicationFiled: June 2, 2020Publication date: September 17, 2020Inventors: Joon-Sung LIM, Jang-Gn YUN, Jaesun YUN
-
Patent number: 10727244Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.Type: GrantFiled: May 17, 2018Date of Patent: July 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Joon-Sung Lim, Eunsuk Cho
-
Publication number: 20200227435Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.Type: ApplicationFiled: November 18, 2019Publication date: July 16, 2020Inventors: Sung Min Hwang, Joon Sung Lim, Woo Sung Yang, Dong Sik Lee
-
Patent number: 10700085Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.Type: GrantFiled: June 18, 2018Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Hwang, Dong-Sik Lee, Joon-Sung Lim
-
Patent number: 10692881Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.Type: GrantFiled: May 17, 2018Date of Patent: June 23, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Joon-Sung Lim, Jihye Kim
-
Publication number: 20200185401Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.Type: ApplicationFiled: February 17, 2020Publication date: June 11, 2020Inventors: Sung-Min Hwang, Jang-Gn Yun, Joon-Sung Lim
-
Publication number: 20200176464Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.Type: ApplicationFiled: July 16, 2019Publication date: June 4, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dong Hoon Jang, Woo Sung YANG, Joon Sung LIM, Sung Min HWANG
-
Publication number: 20200152654Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.Type: ApplicationFiled: July 17, 2019Publication date: May 14, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Min HWANG, Joon-Sung LIM, Jiyoung KIM, Jiwon KIM, Woosung YANG
-
Publication number: 20200144380Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.Type: ApplicationFiled: June 19, 2019Publication date: May 7, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Joon-Sung LIM, Jiyoung KIM, Jiwon KIM, Woosung YANG
-
Publication number: 20200135749Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: ApplicationFiled: August 17, 2019Publication date: April 30, 2020Inventors: SUNG MIN HWANG, JOON SUNG LIM, BUM KYU KANG, JAE HO AHN
-
Publication number: 20200091084Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.Type: ApplicationFiled: November 20, 2019Publication date: March 19, 2020Inventors: Young-woo KIM, Joon-sung LIM, Jang-gn YUN, Sung-min HWANG
-
Patent number: 10593689Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.Type: GrantFiled: August 24, 2017Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sung Song, Jae-Hwang Sim, Joon-Sung Lim
-
Patent number: 10566342Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.Type: GrantFiled: November 7, 2017Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Jang-Gn Yun, Joon-Sung Lim
-
Publication number: 20190393243Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.Type: ApplicationFiled: September 6, 2019Publication date: December 26, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungjoong KIM, Joon-Sung LIM, Sung-Min HWANG