Abstract: A method and system for detecting a fault of a serial coil type permanent magnet motor includes driving the motor based on a predefined current reference value, detecting a phase current vector of the motor, and calculating a current compensation value for removing a negative sequence component of the motor based on the phase current vector. The current compensation value is provided to a negative sequence current controller for calculating a faulty phase and a degree of a fault of the motor using the output of the negative sequence current controller and a fault model to which induced magnetic flux variations in a specific slot of a specific faulty phase of the motor and other slots of the same phase as the specific phase are applied, and applying a current reference value to which the calculated faulty phase and degree of fault are applied.

Abstract: A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.

Abstract: A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.

Abstract: A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.

Abstract: A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.

Abstract: A Time-to-Digital Converter (TDC) is provided.

Abstract: A Time-to-Digital Converter (TDC) is provided.

Abstract: Disclosed is a polytetrafluoroethylene coating agent having low friction and high wear resistance, obtained by dispersing nanodiamond powder in a polar organic solvent, stirring the nanodiamond dispersion solution and a silane coupling agent, and stirring the silane-treated dispersion solution and an oily polytetrafluoroethylene coating solution, in which the silane coupling agent has at least one organic functional group selected from, but not limited to, a mercapto group and an amino group, the organic functional group exhibiting high bondability to polytetrafluoroethylene. A method of preparing the polytetrafluoroethylene coating agent and a method of using the polytetrafluoroethylene coating agent are also provided.