Patents by Inventor Joong-Yun RA

Joong-Yun RA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10453707
    Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Seok Cho, Hyung Joon Kim, Jung Ho Kim, Joong Yun Ra, Bi O Kim, Jae Young Ahn, Ki Yong Oh, Sung Hae Lee
  • Patent number: 10276589
    Abstract: A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung Joon Kim, Yong Seok Cho, BiO Kim, Jung Ho Kim, Joong Yun Ra, Sung Hae Lee
  • Publication number: 20180315621
    Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.
    Type: Application
    Filed: October 24, 2017
    Publication date: November 1, 2018
    Inventors: Yong Seok CHO, Hyung Joon KIM, Jung Ho KIM, Joong Yun RA, Bi O KIM, Jae Young AHN, Ki Yong OH, Sung Hae LEE
  • Patent number: 9991281
    Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Mi Yun, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
  • Publication number: 20180122821
    Abstract: A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.
    Type: Application
    Filed: April 27, 2017
    Publication date: May 3, 2018
    Inventors: Hyung Joon KIM, Yong Seok CHO, BiO KIM, Jung Ho KIM, Joong Yun RA, Sung Hae LEE
  • Publication number: 20170358596
    Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.
    Type: Application
    Filed: August 8, 2017
    Publication date: December 14, 2017
    Inventors: JU-MI YUN, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
  • Patent number: 9754959
    Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: September 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Mi Yun, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
  • Publication number: 20160172372
    Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 16, 2016
    Inventors: JU-MI YUN, YOUNG-JIN NOH, KWANG-MIN PARK, JAE-YOUNG AHN, GUK-HYON YON, DONG-CHUL YOO, JOONG-YUN RA, YOUNG-SEON SON, JEON-IL LEE, HUN-HYEONG LIM
  • Publication number: 20160168704
    Abstract: A gas injector may comprise: a gas introduction tube configured to introduce reaction gas into a reaction tube from a gas supply source; and/or a gas distributor connected to the gas introduction tube, extending from the gas introduction tube in a direction within the reaction tube, including a plurality of ejection holes in an inner surface of the gas distributor, and having an arc shape extending in a circumferential direction of the reaction tube. The ejection holes may be spaced apart from each other in the extending direction of the gas distributor, and are configured to spray the reaction gas.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 16, 2016
    Inventors: Ji-Hoon CHOI, Young-Jin NOH, Joong-Yun RA, Jae-Young AHN, Hun-hyeong LIM