Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).

Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through a lowest of the conductive tiers. The TAV constructions individually comprise an insulative lining having a lowest surface that is directly against metal material in the lowest conductive tier. Other embodiments, including method, are disclosed.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material.

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tiers. A void space is formed directly above the conductor tier laterally-across individual of the memory-block regions. The void space comprises an exposed silicon-containing surface. Conductively-doped silicon is selectively deposited onto and from the exposed silicon-containing surface. The conductively-doped silicon is directly electrically coupled to the channel material of the channel-material strings and is directly electrically coupled to the conductor material of the conductor tier and directly electrically couples the channel-material strings to the conductor material of the conductor tier.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers having channel-material strings therein. Walls are formed above insulating material that is directly above the channel-material strings. Void space is laterally-between immediately-adjacent of the walls and that comprises a longitudinal outline of individual digitlines to be formed. Spaced openings are in the insulating material directly below the void space. Relative to the walls, a conductive metal nitride is selectively deposited in the void space, in the spaced openings, and atop the insulating material laterally-between the walls and the spaced openings to form a lower portion of the individual digitlines laterally-between the immediately-adjacent walls. The conductive metal nitride that is in individual of the spaced openings is directly electrically coupled to individual of the channel-material strings.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Conducting material is formed in one of the first tiers. The conducting material comprises a seam in and longitudinally-along opposing sides of individual of the memory-block regions in the one first tier. The seam is penetrated with a fluid that forms intermediate material in the seam longitudinally-along the opposing sides of the individual memory-block regions in the one first tier and comprises a different composition from that of the conducting material. Other embodiments, including structure independent of method, are disclosed.

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

Abstract: A microelectronic device includes a source stack, a source contact vertically adjacent to the source stack, a semiconductor material vertically adjacent to the source contact, tiers of alternating conductive materials and dielectric materials vertically adjacent to the semiconductor dielectric material, a dielectric structure within a slot structure and extending through the tiers of the microelectronic device to the source contact of the microelectronic device, oxide cap structures laterally between the semiconductor material and the dielectric structure, and pillars extending through the tiers, the semiconductor material, and the source contact and into the source stack. Related electronic systems and methods are also disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches.

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.