Abstract: A secure processing engine and method configured to protect a computing system are provided. The system includes a first processor configured to provide real-time protection to at least processes executed over the main processor of the protected computing system; and a direct memory access (DMA) configured to provide an access to a main memory of the main processor, wherein the first processor is coupled to the DMA and further configured to monitor the at least processes by accessing the main memory via the DMA; wherein the first processor operates in an execution environment in complete isolation from an execution environment of the main processor.

Abstract: A secure processing engine and method configured to protect a computing system are provided. The system includes a first processor configured to provide real-time protection to at least processes executed over the main processor of the protected computing system; and a direct memory access (DMA) configured to provide an access to a main memory of the main processor, wherein the first processor is coupled to the DMA and further configured to monitor the at least processes by accessing the main memory via the DMA; wherein the first processor operates in an execution environment in complete isolation from an execution environment of the main processor.

Abstract: A method, and processor for securing a host platform of a computing device are presented. The method includes generating, by a security processor, a first graph based on at least a portion of executable code, wherein the executable code is executed by a main processor of the host platform; generating a metadata file based on the generated first graph; polymorphing the executable code based on the generated metadata file; generating a second graph based on the polymorphed code; creating slices of the polymorphed code; executing at least one slices of the created slices by the security processor, wherein the security processor is apart from the main processor; polymorphing the at least one of executed slice; and pairing the least polymorphed slice with the polymorphed code.

Abstract: A sanitization circuit for sanitizing and authenticating a semiconductor device and method thereof are provided. The sanitization circuit is integrated in the semiconductor device and includes a memory verification module configured to verify any pre-programmed memory integrated in the semiconductor device; a memory eraser module configured to erase data stored in at least volatile memory accessed by the semiconductor device; and an implanted circuitry detection module configured to detect any unintended circuitry added to the semiconductor device.

Abstract: A method, and processor for securing a host platform of a computing device are presented. The method includes generating, by a security processor, a first graph based on at least a portion of executable code, wherein the executable code is executed by a main processor of the host platform; generating a metadata file based on the generated first graph; polymorphing the executable code based on the generated metadata file; generating a second graph based on the polymorphed code; creating slices of the polymorphed code; executing at least one slices of the created slices by the security processor, wherein the security processor is apart from the main processor; polymorphing the at least one of executed slice; and pairing the least polymorphed slice with the polymorphed code.

Abstract: An attack resilient distributed proactive polymorphic hardware, the including: at least one polymorphic core including at least one polymorphic logic, the at least one polymorphic logic adapted to adjust an implementation of a proactive polymorphic model without changing the contextual functionality of the proactive polymorphic model; a framework list defining at least one policy to be executed by the proactive polymorphic model; and a graph designating a historical description of each of the at least one policy executed by the proactive polymorphic model.

Abstract: A method, and processor for securing a host platform of a computing device are presented. The method includes generating, by a security processor, a first graph based on at least a portion of executable code, wherein the executable code is executed by a main processor of the host platform; generating a metadata file based on the generated first graph; polymorphing the executable code based on the generated metadata file; generating a second graph based on the polymorphed code; creating slices of the polymorphed code; executing at least one slices of the created slices by the security processor, wherein the security processor is apart from the main processor; polymorphing the at least one of executed slice; and pairing the least polymorphed slice with the polymorphed code.

Abstract: A system and method for the generation of a trusted polymorphic and distributed unique hardware identifier (ID) are provided. The method includes checking a device for a current ID; selecting a polymorphic policy setting randomly when no current ID is detected, wherein the polymorphic policy setting defines a functionality of at least one function of the device; selecting functional steps of the at least one function randomly, wherein the functional steps are selected from a number of states of a finite-state machine (FSM) used to construct the at least one function; pairing an output DNA mechanism to the at least one function; and generating the unique ID based on the paired DNA mechanism, its structure and its functional operation.

Abstract: A triple-band antenna for transmitting and receiving low-frequency band signals and high-frequency band signals. The triple-band antenna includes a printed antenna having two wings for transmitting and receiving low-frequency signals; and an antenna array including a plurality of radiating elements being printed on one of the wings of the printed antenna, wherein the antenna array transmits and receives the high-frequency band signals, wherein one of the wings of the printed dipole is a ground for the antenna array.

Abstract: A consumer electronic device having distributed form factor millimeter wave receiver and transmitter comprising a first motherboard part including a baseband module; a second motherboard part including a receive (RX) active antenna, wherein the RX active antenna is connected to the baseband module using a pair of cables; and a third motherboard part including a transmit (TX) active antenna, wherein the TX active antenna is connected to the baseband module using a pair of cables.

Abstract: A consumer electronic device having distributed form factor millimeter wave receiver and transmitter comprising a first motherboard part including a baseband module; a second motherboard part including a receive (RX) active antenna, wherein the RX active antenna is connected to the baseband module using a pair of cables; and a third motherboard part including a transmit (TX) active antenna, wherein the TX active antenna is connected to the baseband module using a pair of cables.

Abstract: A modular wireless docking station for enabling a wireless connection between a computing device and a plurality of peripheral devices. The modular wireless docking station includes a radio plane having at least a wireless transceiver and at least one antenna for communicating with the computing device over a wireless medium; and a plurality of peripheral interface planes for communicating with one or more of the plurality of peripheral devices.

Abstract: A triple-band antenna for transmitting and receiving low-frequency band signals and high-frequency band signals. The triple-band antenna includes a printed antenna having two wings for transmitting and receiving low-frequency signals; and an antenna array including a plurality of radiating elements being printed on one of the wings of the printed antenna, wherein the antenna array transmits and receives the high-frequency band signals, wherein one of the wings of the printed dipole is a ground for the antenna array.

Abstract: A modular wireless docking station for enabling a wireless connection between a computing device and a plurality of peripheral devices. The modular wireless docking station includes a radio plane having at least a wireless transceiver and at least one antenna for communicating with the computing device over a wireless medium; and a plurality of peripheral interface planes for communicating with one or more of the plurality of peripheral devices.

Abstract: A printed circuit board (PCB) assembled to include at least one millimeter wave antenna and a radio frequency integrated circuit (RF IC). The PCB comprises a square-shaped cavity in the PCB, wherein one of the edges of the cavity is substantially parallel to connecting pins of the at least one millimeter wave antenna; a RF IC placed in the cavity, wherein one side of the RF IC including RF pads is substantially at the edge of the cavity that is substantially parallel to the connecting pins; and traces connecting the RF pads and the connecting pins, wherein the connection between the at least one millimeter wave antenna and the RF IC shortens the length of the traces.

Abstract: A consumer electronic device having distributed form factor millimeter wave receiver and transmitter comprising a first motherboard part including a baseband module; a second motherboard part including a receive (RX) active antenna, wherein the RX active antenna is connected to the baseband module using a pair of cables; and a third motherboard part including a transmit (TX) active antenna, wherein the TX active antenna is connected to the baseband module using a pair of cables.

Abstract: Techniques are presented for improving packet detection within a wireless device in the presence of platform noise. In some embodiments, packet detection is carried out by first performing a correlation operation using a signal at an input of a wireless receiver. The result of the correlation may then be compared to a threshold value in order to make a packet arrival decision. The threshold value may be varied during device operation in a manner that enhances packet detection performance.

Abstract: Techniques to detect radar signals in a communication signal for a wireless system are described.

Abstract: Embodiments of the present invention provide a method, apparatus and system of radar detection. The method, according to some demonstrative embodiments of the invention, may include comparing an energy level of signals received over a wireless communication channel to a threshold; during operation of a processor, if the energy level is above the threshold, determining independently of the processor one or more time values related to said signals; and if the energy level decreases to or below the threshold, interrupting the operation of the processor to determine, based on the time values, one or more parameters of a detection time period during which the energy level was above the threshold. Other embodiments are described and claimed.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods for wireless combined-signal communication. For example, a method in accordance with an embodiment of the invention may include transmitting a combined signal over a combined channel by mapping a first block of said combined signal to be carried by a first sub-channel of said combined channel and mapping a second block, substantially identical to said first block, to be carried by a second sub-channel of said combined channel.