Patents by Inventor Jorge Pedro Rodriguez
Jorge Pedro Rodriguez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8508073Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.Type: GrantFiled: July 17, 2012Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Hung-Piao Ma, Alon Naveh, Gil Schwarzband, Annabelle Pratt, Jorge Pedro Rodriguez, Joseph T. Dibene, II, Sean M. Welch, Kosta Luria, Edward R. Stanford
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Publication number: 20130015715Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.Type: ApplicationFiled: July 17, 2012Publication date: January 17, 2013Inventors: Hung-Piao Ma, Alon Naveh, Gil Schwarzband, Annabelle Pratt, Jorge Pedro Rodriguez, Joseph T. Dibene, II, Sean M. WeIch, Kosta Luria, Edward R. Stanford
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Publication number: 20110199153Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.Type: ApplicationFiled: April 26, 2011Publication date: August 18, 2011Inventors: Hung-Piao Ma, Alon Naveh, Gil Schwarzband, Annabelle Pratt, Jorge Pedro Rodriguez, Joseph T. Dibene, II, Sean M. Welch, Kosta Luria, Edward R. Stanford
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Patent number: 7932639Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.Type: GrantFiled: December 31, 2007Date of Patent: April 26, 2011Assignee: Intel CorporationInventors: Hung-Piao Ma, Alon Naveh, Gil Schwarzband, Annabelle Pratt, Jorge Pedro Rodriguez, Joseph T. Dibene, II, Sean M. Welch, Kosta Luria, Edward R. Stanford
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Publication number: 20090167092Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Hung-Piao Ma, Alon Naveh, Gil Schwarzband, Annabelle Pratt, Jorge Pedro Rodriguez, Joseph T. Dibene, II, Sean M. Welch, Kosta Lurla, Edward R. Stanford
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Patent number: 6545346Abstract: An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.Type: GrantFiled: March 23, 2001Date of Patent: April 8, 2003Assignee: Intel CorporationInventors: David G. Figueroa, Debendra Mallik, Jorge Pedro Rodriguez
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Patent number: 6532143Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.Type: GrantFiled: December 29, 2000Date of Patent: March 11, 2003Assignee: Intel CorporationInventors: David G. Figueroa, Kishore K. Chakravorty, Huong T. Do, Larry Eugene Mosley, Jorge Pedro Rodriguez, Ken Brown
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Patent number: 6483692Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).Type: GrantFiled: December 19, 2000Date of Patent: November 19, 2002Assignee: Intel CorporationInventors: David G. Figueroa, Huong T. Do, Jorge Pedro Rodriguez, Michael Walk
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Publication number: 20020135053Abstract: An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.Type: ApplicationFiled: March 23, 2001Publication date: September 26, 2002Inventors: Dave G. Figueroa, Debendra Mallik, Jorge Pedro Rodriguez
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Publication number: 20020085334Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.Type: ApplicationFiled: December 29, 2000Publication date: July 4, 2002Applicant: Intel CorporationInventors: David G. Figueroa, Kishore K. Chakravorty, Huong T. Do, Larry Eugene Mosley, Jorge Pedro Rodriguez, Ken Brown
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Publication number: 20020075630Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).Type: ApplicationFiled: December 19, 2000Publication date: June 20, 2002Applicant: Intel CorporationInventors: David G. Figueroa, Huong T. Do, Jorge Pedro Rodriguez, Michael Walk