Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.