Abstract: A device (10) to detect and measure static electric charge (q) on an object (100) being positioned in a distance (r.) from an input electrode (11) of the device (10) comprises at least one MOS field transistor (20). The input electrode (11) is connected with the gate electrode (21) of the MOS-FET (20) to detect said electrical charge. The MOS-FET (20) can comprise a gate oxide layer underneath the gate (21) and over the source (22) and drain (23) areas having a sufficient thickness to allow the MOS field transistor (20) to withstand several kilovolts (kV) of voltage and to avoid the loss of charges by tunnel effect due to the high potential of the gate electrode during ESD events.

Abstract: A device (10) to detect and measure static electric charge (q) on an object (100) being positioned in a distance (r.) from an input electrode (11) of the device (10) comprises at least one MOS field transistor (20). The input electrode (11) is connected with the gate electrode (21) of the MOS-FET (20) to detect said electrical charge. The MOS-FET (20) can comprise a gate oxide layer underneath the gate (21) and over the source (22) and drain (23) areas having a sufficient thickness to allow the MOS field transistor (20) to withstand several kilovolts (kV) of voltage and to avoid the loss of charges by tunnel effect due to the high potential of the gate electrode during ESD events.

Abstract: A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.

Abstract: An erasable and programmable non-volatile cell, comprising a first transistor having a source, a drain and a gate; a floating capacitor having a floating gate and a control gate, said floating gate being connected to said gate of said first transistor; and means to detect the state, whether erased or programmed, of the cell; is characterized in that said means to detect the state of the cell comprises a second transistor having a source, a drain and a gate, said second transistor being complementary to said first transistor and said gate of said second transistor being connected to said floating gate.

Abstract: A chip with at least two metal bumps (6a, 6b) which has insulation layers for opposing side walls which are deposited in a plasma activated gas. Predetermined portions of the insulation layer (7) are removed by reactive ion etching. The metal bumps can be formed of a noble metal and the insulation layer of a dielectric material such as SiO2Si3N4.

Abstract: An Erasable and programmable non-volatile cell, comprising a first transistor having a source, a drain and a gate; a floating capacitor having a floating gate and a control gate, said floating gate being connected to said gate of said first transistor; and means to detect the state, whether erased or programmed, of the cell; is characterized in that said means to detect the state of the cell comprises a second transistor having a source, a drain and a gate, said second transistor being complementary to said first transistor and said gate of said second transistor being connected to said floating gate.

Abstract: An arrangement comprising a substrate, a capacitor, an interconnection layer and a contact structure, wherein the capacitor comprises a first electrode (6) and a second electrode (9) and also an interposed dielectric (8), the contact structure comprises a UBM (under-bump metallization) layer (9) and a bump contact (10), the interconnection layer (6) forms the first electrode of the capacitor, and the UBM layer (9) forms the second electrode of the capacitor.

Abstract: The invention describes an assembly provided with a component and a substrate (7). The component and the substrate (7) are electrically interconnected by means of connecting structures (6, 8). The first connecting structure (6) of the component comprises aluminum, which simplifies the manufacture of the assembly.

Abstract: Text Integrated circuit device (20) comprising a silicon substrate (21), integrated devices (22) with contacts (23.1, 23.2), an isolating layer (24) at least partially covering the integrated devices (22) and comprising conducting areas (24.1, 24.2) which establish a conductive path to the contacts (23.1, 23.2) of the integrated devices (22). A metallization level (25) with metal lines (26.1, 26.2, 26.3, 26.4) is provided which connect to one of the contacts (23.2). The metal lines (26.1, 26.2, 26.3, 26.4) are situated above the isolating layer (24). A passivation layer (27)—situated above the metallization level (25)—comprises at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4). A bump bridge (29) comprising a conductive, low-resistance material, is situated on the passivation layer (27). The bump bridge (29) has a high aspect ratio and provides for a conductive connection between at least two of the metal lines (26.2, 26.4).

Abstract: The invention relates to an integrated circuit device comprising a circuit provided in an active circuit area (4) at a surface of a semiconductor body (1). The circuit comprises circuit devices (2, 3) and an interconnect structure (8) comprising at least one patterned metal layer (5, 6) for interconnecting circuit devices (2, 3) so as to form the circuit. The patterned metal layer (5, 6) is disposed over the circuit devices (2, 3). The circuit further comprises a layer of passivating material (9) disposed atop the interconnect structure (8) and a bump electrode (11, 12, 13) for connection of the circuit to the outside world. The bump electrode (11, 12, 13) lies substantially perpendicularly above the active circuit area (4). According to the invention, the circuit devices (2, 3) are substantially directly electrically connected to the bump electrode (11, 12, 13) by means of an electrical connection (10) extending from the interconnect structure (8) and passing through the layer of passivating material (9).

Abstract: The invention describes an assembly provided with a component and a substrate (7). The component and the substrate (7) are electrically interconnected by means of connecting structures (6, 8). The first connecting structure (6) of the component comprises aluminum, which simplifies the manufacture of the assembly.

Abstract: A method of manufacturing a programmable semiconductor element in the form of an anti-fuse, comprising a thin layer of silicon oxide between two electrode regions, such that a connection can be formed between these electrode regions through electric breakdown in the oxide. In the method, a nitrogen implantation is first carried out at the area of the oxide to be formed, so that a thin layer comprising nitrogen is formed at the surface, which has an oxidation-decelerating effect. Then the oxide is provided through thermal oxidation. Owing to the oxidation-decelerating effect of the layer with nitrogen, an extremely thin oxide layer, for example 5 nm thick, may be obtained in a reproducible manner in a sufficiently long oxidation time.

Abstract: A method of manufacturing a semiconductor device having a field effect transistor and a device manufactured by this method in which a high packing density can be realized. The field effect transistor includes a gate electrode (31,41) which is separated from a channel region by a first insulating layer (8) and is entirely surrounded by insulating material. For this purpose, a conductive layer (9) which is to form a gate electrode (31,41) is covered with a second insulating layer (10) and both layers are subsequently given the same pattern at least at the area of the channel region. As a result, the gate electrode (31,41) is covered at the upper side with a portion of the second insulating layer (10). The gate electrode (31,41) is laterally insulated by the provision of a third insulating layer (13) which is subsequently etched back anisotropically, whereby a portion (14) thereof remains intact afterwards alongside the side wall of the gate electrode (31,41).

Abstract: A method of manufacturing an integrated circuit having at least an insulated gate field effect transistor (IGFET). Provided on the silicon surface are successively a gate oxide layer and a doped silicon layer which are patterned by etching by means of a silicon nitride-containing mask which comprises the gate electrode(s) and interconnections. Nitrogen ions are implanted in the surface parts not underlying the mask. By thermal oxidation only the edges of the silicon pattern are oxidized. By ion implantation the source and drain zones are formed, the gate electrodes serving as an implantation mask. If desired, the threshold voltage may then be adjusted by ion implantation in the channel region via the gate electrode.

Abstract: A method of manufacturing a semiconductor device having at least one insulated gate field effect transistor in which a silicon body is provided with a silicon dioxide gate insulation layer and in which a boron-doped polysilicon electrode layer is formed on said layer, characterized in that the electrode layer is deposited by means of a low-pressure process, that the boron doping of the electrode layer is obtained by ion implantation, and that the silicon body is then subjected to a thermal treatment in an atmosphere containing hydrogen in which boron is diffused from the electrode layer through the gate insulation layer into a channel region underlying the electrode layer.

Abstract: A method of manufacturing a semiconductor device, in particular a device having two complementary insulated gate field effect transistors, in which an aperture is provided in a masking layer and in said aperture a zone is diffused in the body from a highly doped layer, in particular a phosphorus glass layer. According to the invention, a thermal oxide layer is formed in the aperture in a first heating step during the diffusion, after which the doping layer is removed without using a mask and while maintaining the thermal oxide layer, and the dopant is then further diffused in a second heating step. The thermal oxide layer serves as a partial masking against the diffusion, as an etchant stopper and in many cases also as a mask against ion implantation.