Patents by Inventor Joseph A. De Santis

Joseph A. De Santis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352522
    Abstract: Semiconductor devices for high frequency operations are described. The semiconductor devices include a substrate with an epitaxial layer. The epitaxial layer has higher resistivity than the substrate and includes a surface facing away from the substrate. The epitaxial layer includes a shallow trench isolation (STI) structure extended to a first depth from the surface, which is surrounded by a well structure. Underneath the STI structure, the epitaxial layer includes a lightly doped portion exclusive of dopant atoms of the well structure. Moreover, the STI structure includes an inner portion surrounded by a deep trench isolation structure extended to a second depth from the surface, the second depth being greater than the first depth. An integrated circuit component is located above the inner portion of the STI structure.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Mattias Dahlstrom, Joseph De Santis, Jeffrey A. Babcock
  • Patent number: 7633373
    Abstract: A thin film resistor is formed to have very accurately defined dimensions which, in turn, allow the resistive value of the resistor to be very accurately defined. The resistor is formed on spaced-apart conductive pads which, in turn, are electrically connected to conductive plugs that are spaced apart from the resistor.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: December 15, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Joseph A. De Santis, Richard Wendell Foote, Jr.
  • Patent number: 7422366
    Abstract: A current mirror method is provided that can be utilized to evaluate thermal issues is silicon-on-insulator (SOI) bipolar junction transistors (BJTs). The method significantly improves safe operating area (SOA) measurement sensitivity. Unlike conventional methods, the current mirror method can provide quantitative analysis of the BJTs thermal instability over a wide power range, even in the apparent SOA of the device. This method can also predict and evaluate SOA with respect to emitter ballast resistance and current crowding.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: September 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Jonggook Kim, Yun Liu, Joseph A De Santis
  • Patent number: 6931345
    Abstract: A method for quantifying safe operating regions within a safe operating area (SOA) for a bipolar junction transistor (BJT) by driving the device under test (DUT) as part of a current mirror circuit and monitoring variances in the current mirror ratio for various biasing conditions.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Jonggook Kim, Yun Liu, Joseph A. De Santis