Patents by Inventor Joseph Cox Ballantyne

Joseph Cox Ballantyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7680285
    Abstract: A system and method for adaptive estimation and compensation of clock drift in echo cancellers is provided. The invention includes an acoustic echo cancellation system with a built in adaptive clock drift compensation system. The acoustic echo cancellation system has an AEC component that performs acoustic echo cancellation on data from a capture buffer, by also using information derived from a render buffer. The clock drift compensation system has access to this capture buffer and render buffer. The clock drift compensation system includes a clock drift compensator that calculates, based on the current location of the capture data being processed by the AEC component as well as additional information, the ideal location in the render buffer from which the AEC component should process data. The clock drift compensator further adjusts the current location in the render buffer from which the AEC component processes data based, at least in part, upon this ideal location.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: March 16, 2010
    Assignee: Microsoft Corporation
    Inventors: Joseph Cox Ballantyne, Jack Wilson Stokes, III, Henrique Malvar
  • Patent number: 7120259
    Abstract: A system and method for adaptive estimation and compensation of clock drift in echo cancellers is provided. The invention includes an acoustic echo cancellation system with a built in adaptive clock drift compensation system. The acoustic echo cancellation system has an AEC component that performs acoustic echo cancellation on data from a capture buffer, by also using information derived from a render buffer. The clock drift compensation system has access to this capture buffer and render buffer. The clock drift compensation system includes a clock drift compensator that calculates, based on the current location of the capture data being processed by the AEC component as well as additional information, the ideal location in the render buffer from which the AEC component should process data. The clock drift compensator further adjusts the current location in the render buffer from which the AEC component processes data based, at least in part, upon this ideal location.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: October 10, 2006
    Assignee: Microsoft Corporation
    Inventors: Joseph Cox Ballantyne, Jack Wilson Stokes, III, Henrique S. Malvar
  • Patent number: 6681192
    Abstract: Systems and methods for efficiently and accurately determining a speed of a faster clock having unknown frequency using a slower clock having a known frequency. A series of measurement pairs are taken from the clocks; each measurement pair including one measurement from the slower clock and one measurement—at the same time—from the faster clock. A lower bound and an upper bound for the measurement pairs are determined. The lower bound and the upper bound are averaged to derive a calibration variable that indicates a number of clock cycles that occur on the faster clock during one cycle of the slower clock. The calibration variable is used to time various processes in a computer system.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: January 20, 2004
    Assignee: Microsoft Corporation
    Inventor: Joseph Cox Ballantyne
  • Publication number: 20020038190
    Abstract: Systems and methods for efficiently and accurately determining a speed of a faster clock having unknown frequency using a slower clock having a known frequency. A series of measurement pairs are taken from the clocks; each measurement pair including one measurement from the slower clock and one measurement—at the same time—from the faster clock. A lower bound and an upper bound for the measurement pairs are determined. The lower bound and the upper bound are averaged to derive a calibration variable that indicates a number of clock cycles that occur on the faster clock during one cycle of the slower clock. The calibration variable is used to time various processes in a computer system.
    Type: Application
    Filed: September 24, 2001
    Publication date: March 28, 2002
    Inventor: Joseph Cox Ballantyne