Abstract: An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.

Abstract: A method for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The new method produces significantly larger tunneling currents for a given voltage than attained in prior work. The new method is advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs). These FLOTOX transistors are candidates for replacing the low power operation transistors found in DRAMs.

Abstract: A microcavity discharge device generates radiation with wavelengths in the range of from 11 to 14 nanometers. The device has a semiconductor plug, a dielectric layer, and an anode layer. A microcavity extends completely through the anode and dielectric layers and partially into the semiconductor plug. According to one aspect of the invention, a substrate layer has an aperture aligned with the microcavity. The microcavity is filled with a discharge gas under pressure which is excited by a combination of constant DC current and a pulsed current to produce radiation of the desired wavelength. The radiation is emitted through the base of the microcavity. A second embodiment has a metal layer which transmits radiation with wavelengths in the range of from 11 to 12 nanometers, and which excludes longer wavelengths from the emitted beam.

Abstract: A surface-transformation method of forming regions of a second material in a first solid material to control the properties of the first solid material is disclosed. The regions of the second material are formed in the first solid material by drilling holes to a predefined depth and at a predefined lattice position. The holes in the first solid material are then filled with a second material and then the first and second materials are heated to a temperature close to the melting point of the first solid material to spontaneously form the regions filled with the second material and embedded in the first solid material at the desired location. A liquid-phase immersion method or a deposition method may be employed to fill the holes in the first solid material.

Abstract: A microcavity discharge device generates radiation with wavelengths in the range of from 11 to 14 nanometers. The device has a semiconductor plug, a dielectric layer, and an anode layer. A microcavity extends completely through the anode and dielectric layers and partially into the semiconductor plug. According to one aspect of the invention, a substrate layer has an aperture aligned with the microcavity. The microcavity is filled with a discharge gas under pressure which is excited by a combination of constant DC current and a pulsed current to produce radiation of the desired wavelength. The radiation is emitted through the base of the microcavity. A second embodiment has a metal layer which transmits radiation with wavelengths in the range of from 11 to 12 nanometers, and which excludes longer wavelengths from the emitted beam.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC manufacturing. The apparatus comprises a reaction chamber with a high intensity UV light source and a wafer holder in the chamber. The UV light source is made of arrays of microdischarge devices fabricated on a semiconductor wafer where each of the microdischarge devices has the structure of a hollow cathode. Multiple arrays of microdischarge devices can be assembled together to make a planar UV lamp so as to provide a sufficient area for the UV illumination. The wafer holder in the chamber is made rotatable for a better uniformity during the photoreduction process. A non-oxidizing gas is flowed into the chamber to prevent instant and subsequent oxidation on the copper surface.

Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

Abstract: A surface-transformation method of forming regions of a second material in a first solid material to control the properties of the first solid material is disclosed. The regions of the second material are formed in the first solid material by drilling holes to a predefined depth and at a predefined lattice position. The holes in the first solid material are then filled with a second material and then the first and second materials are heated to a temperature close to the melting point of the first solid material to spontaneously form the regions filled with the second material and embedded in the first solid material at the desired location. A liquid-phase immersion method or a deposition method may be employed to fill the holes in the first solid material.

Abstract: The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.

Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material.

Abstract: Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.

Abstract: A photonic crystal optical fiber made up of an array of conventional hollow core optical fibers is disclosed. The array of optical fibers omits at least one fiber to form a central hollow core. The fiber works on the principle of two-dimensional photonic crystals to confine the radiation in a guided wave within the central hollow core. The fiber has a true photonic bandgap in which radiation of a particular energy or wavelength is totally forbidden, thereby providing a very high reflection coefficient to radiation incident the walls of the central hollow core over a select range of angles. The central hollow core allows for radiation propagation with minimal absorption.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material. (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.

Abstract: A waveguide structure formed with a three-dimensional (3D) photonic crystal is disclosed. The 3D photonic crystal comprises a periodic array of voids formed in a solid substrate. The voids are arranged to create a complete photonic bandgap. The voids may be formed using a technique called “surface transformation,” which involves forming holes in the substrate surface, and annealing the substrate to initiate migration of the substrate near the surface to form voids in the substrate. A channel capable of transmitting radiation corresponding to the complete bandgap is formed in the 3D photonic crystal, thus forming the waveguide. The waveguide may be formed by interfacing two 3D photonic crystal regions, with at least one of the regions having a channel formed therein. The bandgap wavelength can be chosen by arranging the periodic array of voids to have a lattice constant a fraction of the bandgap wavelength.

Abstract: A method of forming a three-dimensional (3D) complete photonic bandgap crystal by crystal modification is disclosed. The 3D crystal includes a first periodic array of unit cells formed from first voids connected by imaginary bonds. The first periodic array forms an incomplete bandgap. The first voids may be formed in any one of a number of shapes, including spherical. The 3D crystal further includes a second periodic array of second voids. The second voids are arranged along the imaginary bonds so as to modify each unit cell. The modification of the unit cells is designed to form a complete photonic bandgap.