Abstract: A system, method, and/or non-transitory computer readable medium may implement or be configured to implement the following computational operations associated with electrochemical or vapor phase deposition: (a) defining an interface of a substrate where deposition of a deposited material is to occur or is occurring; (b) using a computational model of the deposition to determine a local deposition rate of the deposited material at multiple locations on the interface, where the computational model of the deposition computes the local deposition rate as a function of one or more geometric parameters of the one or more recessed or protruding features; and (c) computationally adjusting the location of the interface to produce an adjusted interface.

Abstract: An illustrative example embodiment of a device that facilitates administering a fluid into an individual's body tissue includes an ultrasound transducer configured to emit sound waves and detect reflected sound waves. At least one processor is configured to: control operation of the ultrasound transducer in a first mode for detecting a condition of the individual's body tissue, determine a suitable administration site based on the transducer operating in the first mode, instigate an indication regarding the suitable administration site, and control operation of the ultrasound transducer in a second, different mode for enhancing absorption of the fluid at the suitable administration site.

Abstract: Systems and methods for performing local Critical Dimension Uniformity (CDU) modeling in a virtual fabrication environment are discussed. More particularly, local CD variance is replicated in the virtual fabrication environment in order to produce a CDU mask that can be used during a virtual fabrication sequence to produce more accurate results reflecting the CD variance of features that occurs in a pattern for a semiconductor device being physically fabricated.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: Systems and methods for performing reflow modeling in a virtual fabrication environment are discussed. More particularly, the virtual fabrication environment may determine metal or material “reflow” or movement during fabrication of a semiconductor device structure. A reflow modeling step with user-specified parameters may be inserted into a process sequence used during fabrication of the semiconductor device structure.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: An electronic angle adjustment mechanism for a pump and a motor generally includes a base and a linear actuator. The base has an upper portion mounted to a motor, a lower portion mounted to a pump, and a hinge for pivotably moving the upper base portion in relation to the lower base portion. The linear actuator is mounted to on an attachment plate that also attaches the motor to the upper base portion. The linear actuator can drive a flexible member or connect to a gear wheel or worm screw to pivot about the hinge and change an angle between the upper and lower base portions.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A six transistor SRAM memory cell design is discussed. An SRAM memory cell includes criss-crossed transistors in cross-coupled inverters to achieve a more compact form factor and simplify fabrication.

Abstract: A liquid pump having a pump liner and a pump piston, wherein the pump liner defines a central longitudinal bore and a transverse inlet bore communicating with the central bore for conveying a liquid. The pump piston has a centerline intersecting with a centerline of the transverse inlet bore, and further has a flat surface formed parallel with the piston centerline at a distal end of the piston. The flat surface defines a cut-out portion of the piston, wherein the cut-out portion has a hydraulic diameter equal to the diameter of the transverse inlet bore of the liner, and a distance from the centerline of the piston to the flat surface defining the cut-out portion is greater than or equal to ½ of the diameter of the transverse inlet bore of the liner.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A six transistor SRAM memory cell design is discussed. An SRAM memory cell includes criss-crossed transistors in cross-coupled inverters to achieve a more compact form factor and simplify fabrication.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: A liquid pump having a pump liner and a pump piston, wherein the pump liner defines a central longitudinal bore and a transverse inlet bore communicating with the central bore for conveying a liquid. The pump piston has a centerline intersecting with a centerline of the transverse inlet bore, and further has a flat surface formed parallel with the piston centerline at a distal end of the piston. The flat surface defines a cut-out portion of the piston, wherein the cut-out portion has a hydraulic diameter equal to the diameter of the transverse inlet bore of the liner, and a distance from the centerline of the piston to the flat surface defining the cut-out portion is greater than or equal to ½ of the diameter of the transverse inlet bore of the liner.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.