Abstract: The present disclosure provides macrocyclic compounds inspired by the immunophilin ligand family of natural products FK506 and rapamycin. The generation of a Rapafucin library of macrocyles that contain FK506 and rapamycin binding domains should have great potential as new leads for developing drugs to be used for treating diseases.

Abstract: This invention relates to novel whitening agents for cellulosic substrates. The whitening agents are comprised of at least two components: at least one chromophore component and at least one polymeric component. Suitable chromophore components generally fluoresce blue, red, violet, or purple color when exposed to ultraviolet light, or they may absorb light to reflect these same shades. The whitening agents are further characterized by having a dispersion component value of the Hansen Solubility Parameter of less than or equal to about 17 MPa0.5. This invention also relates to laundry care compositions including but not limited to liquid and/or powder laundry detergent formulations and rinse added fabric softening (RAFS) compositions that comprise such whitening agents.

Abstract: A rotor assembly of a generator includes a rotor core including a plurality of core poles defining a plurality of core slots therebetween. The core poles extend from a first axial end of the rotor core to a second axial end of the rotor core. A rotor winding is installed to the rotor core and has a plurality of core segments located in the plurality of core slots, and a plurality of end turns connecting the plurality of core segments. An end plate is located at at least one of the first axial end or the second axial end and includes a plate portion and a plurality of wedge ends extending from the plate portion. Each wedge end is located at a corresponding core slot. The end plate is supportive of the plurality of end turns of the rotor winding.

Abstract: A rotor assembly of a generator includes a rotor core including a plurality of core poles defining a plurality of core slots therebetween. The core poles extend from a first axial end of the rotor core to a second axial end of the rotor core. A rotor winding is installed to the rotor core and has a plurality of core segments located in the plurality of core slots, and a plurality of end turns connecting the plurality of core segments. An end plate is located at at least one of the first axial end or the second axial end and includes a plate portion and a plurality of wedge ends extending from the plate portion. Each wedge end is located at a corresponding core slot. The end plate is supportive of the plurality of end turns of the rotor winding.

Abstract: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size.

Abstract: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size.

Abstract: Bitcell layouts for use in electronic devices and systems are described. One embodiment relates to a memory including at least one bitcell, the bitcell including a storage cell region and a read channel region. The storage cell region is substantially L-shaped and includes six transistors. The read channel region is shaped to fit together with the substantially L-shaped storage cell region to form a substantially rectangular bitcell shape. Other embodiments are described and claimed.

Abstract: Bitcell layouts for use in electronic devices and systems are described. One embodiment relates to a memory including at least one bitcell, the bitcell including a storage cell region and a read channel region. The storage cell region is substantially L-shaped and includes six transistors. The read channel region is shaped to fit together with the substantially L-shaped storage cell region to form a substantially rectangular bitcell shape. Other embodiments are described and claimed.

Abstract: A storage cell having a storage circuit and a readout circuit may be used in power-saving environments, where the storage circuit may be maintained in an ultra-drowsy mode during power-saving periods while the readout circuit may be powered down during power-saving periods. A pull-down transistor may be incorporated into the readout circuit to reduce current leakage during power-saving periods.

Abstract: A storage cell having a storage circuit and a readout circuit may be used in power-saving environments, where the storage circuit may be maintained in an ultra-drowsy mode during power-saving periods while the readout circuit may be powered down during power-saving periods. A pull-down transistor may be incorporated into the readout circuit to reduce current leakage during power-saving periods.

Abstract: A method for designing an integrated circuit die having bi-directional I/O buffers shared by multiple designs therein. The multi-design integrated circuit die is designed by combining netlists, each of which represents a complete design, and pin-pad assignment lists for the individual designs into a top-level consolidated netlist or multi-design netlist with its own consolidated pin-pad assignment. Data for the top-level consolidated design, including stimulus vectors and response vectors, are used to generate a semiconductor test program to test the integrated circuit die. Consolidation of netlist, pin-pad assignments and vectors are accomplished using design automation software and techniques. The top-level consolidated design data may include configuration information externally applied to the consolidated design.

Abstract: A method for designing an integrated circuit die having bi-directional I/O buffers shared by multiple designs therein. The multi-design integrated circuit die is designed by combining netlists, each of which represents a complete design, and pin-pad assignment lists for the individual designs into a top-level consolidated netlist or multi-design netlist with its own consolidated pin-pad assignment. Data for the top-level consolidated design, including stimulus vectors and response vectors, are used to generate a semiconductor test program to test the integrated circuit die. Consolidation of netlist, pin-pad assignments and vectors are accomplished using design automation software and techniques. The top-level consolidated design data may include configuration information externally applied to the consolidated design.

Abstract: A multi-design integrated circuit having I/O buffers that are shared by multiple designs in the integrated circuit, the multi-design integrated circuit being designed by combining netlists and pin-pad assignment lists for the individual designs into one overall netlist or multi-design netlist.

Abstract: A main body portion of a shoe includes a base having a heel and a sole, and an upper on the base. A lower sole is positioned below the base sole and is movable front to rear and back relative to the base sole. A transducer is provided in the seal and is connected to the lower sole. The transducer pushes the lower sole forwardly in response to heel pressure being imposed by the heel of the wearer on the heel of the shoe. After a forward shoe is set down on the ground, with its heel up and its lower sole contacting the ground, the main body portion of the shoe, with the wearer's foot inside of it, slides forward and adds length to the step.

Abstract: A golf club of the type for putting and driving a golf ball. The golf club has a reflective surface which is positionable to direct toward a golfer's eye an alignment image including an image of the ball and the target into which the ball is directed so as to aid the golfer in positioning the head of the golf club relative to the ball. The reflective surface is removable from the head so as to be stowed when not in use. The golf club also includes a leveling device in the head of the club to indicate to the golfer when the head is aligned horizontally. The golf club further includes a first striking surface with a tilted striking surface portion for imparting spin to the golf ball, and a second striking surface opposite the first for directing the ball in an upward trajectory. The tilted striking surface may include a flat central portion and an adjacent flat end portion, both of which contact the golf ball.