Patents by Inventor Joseph I. Chamdani

Joseph I. Chamdani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7460528
    Abstract: Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A storage resource identifier corresponding to the target identifier is determined according to a forwarding table. A sequence identifier is associated with the source identifier, where the sequence identifier corresponds to the target. The source identifier and the sequence identifier are recorded at a context table, and the data packet is routed according to the storage resource identifier.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: December 2, 2008
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Joseph I. Chamdani, Litko Chan, Richard D. Reohr, Jr., Wilson K. Yee
  • Patent number: 7433351
    Abstract: Switching data packets includes forwarding first data packets to a first port that is associated with a first domain. Second data packets are forwarded to a second port that is associated with a second domain. The first data packets are managed using a first management subsystem of a service processor card, and the second data packets are managed using a second management subsystem of the service processor card.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: October 7, 2008
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Joseph E. Pelissier, Vikas Deolaliker, Joseph I. Chamdani, Litko Chan, Gurumurthy D. Ramkumar, Rajasekhar Cherabuddi
  • Publication number: 20080189252
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: August 27, 2007
    Publication date: August 7, 2008
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Publication number: 20080189251
    Abstract: Embodiments of the present invention provide processing elements that are capable of performing high level database operations in hardware based on machine code instructions. These processing elements employ a dataflow architecture that operates on data in hardware without interruption or software. A scanning/indexing processing element may comprise logic that analyze database column groups stored in local memory, perform parallel field extraction and comparison, and generates a list of row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy an applied predicate. The scanning/indexing processing may also be used to project database column groups, search and join index structures, and manipulate in-flight metadata flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results.
    Type: Application
    Filed: August 27, 2007
    Publication date: August 7, 2008
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, James Shau, Ravi Krishnamurthy, Joseph I. Chamdani
  • Publication number: 20080183688
    Abstract: Embodiments of the present invention provide a database system that is optimized by using hardware acceleration. The system may be implemented in several variations to accommodate a wide range of queries and database sizes. In some embodiments, the system may comprise a host system that is coupled to one or more hardware accelerator components. The host system may execute software or provide an interface for receiving queries. The host system analyzes and parses these queries into tasks. The host system may then select some of the tasks and translate them into machine code instructions, which are executed by one or more hardware accelerator components. The tasks executed by hardware accelerators are generally those tasks that may be repetitive or processing intensive. Such tasks may include, for example, indexing, searching, sorting, table scanning, record filtering, and the like.
    Type: Application
    Filed: August 27, 2007
    Publication date: July 31, 2008
    Inventors: Joseph I. Chamdani, Raj Cherabuddi, Michael Corwin, Jeremy Branscome, Liuxi Yang, Ravi Krishnamurthy
  • Patent number: 7382776
    Abstract: Routing a data packet includes receiving at a switch a data packet from a storage client. The data packet is associated with a destination identifier identifying a virtual target, where the virtual target is accessible by the storage client. A storage resource identifier corresponding to the destination identifier is determined according to a forwarding table at the switch. The data packet is routed according to the storage resource identifier.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: June 3, 2008
    Assignee: Brocade Communication Systems, Inc.
    Inventors: Litko Chan, Richard D. Reohr, Jr., Joseph I. Chamdani
  • Patent number: 7316021
    Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: January 1, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: William N. Joy, Marc Tremblay, Gary Lauterbach, Joseph I. Chamdani
  • Patent number: 7194550
    Abstract: A unified networking device communicates directly with storage devices and servers in the data center and communicates directly with switches and routers outside of the data center environment. The unified networking device manages data transfers between storage devices, between a storage device and a server, between a storage device and a web switch, and between a storage device and a router. The unified networking device is configured to perform data transfers while bypassing a server. The unified networking device is further configured to perform multi-protocol conversion.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: March 20, 2007
    Assignee: Sanera Systems, Inc.
    Inventors: Joseph I. Chamdani, Raj Cherabuddi, Sudhakar Muddu
  • Patent number: 7185185
    Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: February 27, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: William Joy, Marc Tremblay, Gary Lauterbach, Joseph I. Chamdani
  • Patent number: 7133416
    Abstract: Converting data signals includes determining whether a coupled interface converter paddle coupled to a serdes is a first interface converter paddle or a second interface converter paddle. The first interface converter paddle is associated with a first communication protocol, and the second interface converter paddle is associated with a second communication protocol. The communication protocol associated with the coupled interface converter paddle is identified. Data signals are received from the coupled interface converter paddle, and deserialized according to the identified communication protocol.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: November 7, 2006
    Assignee: McData Corporation
    Inventors: Joseph I. Chamdani, Matthew S. Rogge, Peter Gunadisastra, Jayarama N. Shenoy, Tsuei-chieh Chiu
  • Patent number: 7120915
    Abstract: A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: October 10, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Gajendra P. Singh, Joseph I. Chamdani, Renu Raman, Rabin A. Sugumar
  • Patent number: 7110394
    Abstract: A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: September 19, 2006
    Assignee: Sanera Systems, Inc.
    Inventors: Joseph I. Chamdani, Michael Corwin, Matthew Rogge
  • Patent number: 7088735
    Abstract: Processing a data packet in a multiple protocol system area network is disclosed. A paddle card comprising a first paddle card that supports a first communication protocol or a second paddle card that supports a second communication protocol is received. The communication protocol supported by the received paddle card is identified. Data packets from the received paddle card are processed according to the identified communication protocol.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: August 8, 2006
    Assignee: Sanera Systems, Inc.
    Inventors: Richard D. Reohr, Jr., Joseph E. Pelissier, Joseph I. Chamdani
  • Patent number: 6985975
    Abstract: A device for ensuring reliable data packet throughput in a redundant system includes a splitter that creates copies of a data packet and sends each copy to a separate intermediate source for processing, parallel buffers for receiving the processed packets from the intermediate sources, and a comparator for determining whether the data packets are equivalent.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: January 10, 2006
    Assignee: Sanera Systems, Inc.
    Inventors: Joseph I. Chamdani, Michael Corwin
  • Patent number: 6968491
    Abstract: Generating a check matrix includes defining a set of column vectors. A matrix operable to have a plurality of entries is initiated. Each entry has a submatrix that includes a function of a subset of the set of column vectors. The following is repeated until a last entry of the matrix is reached. Subsets of the set of column vectors are generated from the set of column vectors, and an entry is generated from each subset. A weight associated with each entry is calculated, and an entry having a minimum weight is selected. The selected entry is added to the matrix, and the subset of column vectors associated with the selected entry is removed from the set of column vectors. The matrix is reported.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: November 22, 2005
    Assignee: Sanera Systems Inc.
    Inventors: Liuxi Yang, Yu Fang, Ulrich Stern, Joseph I. Chamdani
  • Patent number: 6938147
    Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: August 30, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: William N. Joy, Marc Tremblay, Gary Lauterbach, Joseph I. Chamdani
  • Patent number: 6920588
    Abstract: Transmitting data includes receiving a serial sequence of code words. Each code word includes a word and check bits, where the word includes a sequence of word symbols, and the check bits includes a sequence of check bit symbols. The following is repeated until a last word symbol of a last code word is reached: selecting a next code word, and inserting a next word symbol of the selected code word into a vector. The following is repeated until a last check bit symbol of the last code word is reached: selecting a next code word, and inserting a next check bit symbol of the selected code word into the vector. The vector is transmitted.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: July 19, 2005
    Assignee: Sanera Systems Inc.
    Inventors: Liuxi Yang, Yu Fang, Ulrich Stern, Joseph I. Chamdani
  • Patent number: 6920601
    Abstract: Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of check matrix columns is generated, where each check matrix column includes a matrix having a subset of the set of primitive elements. A check matrix is generated from a subset of the set of check matrix columns, where the check matrix yields a syndrome that comprises an error pattern for the word. The check matrix is reported.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: July 19, 2005
    Assignee: Sanera Systems Inc.
    Inventors: Ulrich Stern, Joseph I. Chamdani, Yu Fang, Liuxi Yang
  • Patent number: 6801997
    Abstract: A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: October 5, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: William N. Joy, Marc Tremblay, Gary Lauterbach, Joseph I. Chamdani
  • Publication number: 20040162971
    Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 19, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: William N. Joy, Marc Tremblay, Gary Lauterbach, Joseph I. Chamdani