Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

Abstract: Embodiments of the present invention provide a run-time scheduler that schedules tasks for database queries on one or more execution resources in a dataflow fashion. In some embodiments, the run-time scheduler may comprise a task manager, a memory manager, and hardware resource manager. When a query is received by a host database management system, a query plan is created for that query. The query plan splits a query into various fragments. These fragments are further compiled into a directed acyclic graph of tasks. Unlike conventional scheduling, the dependency arc in the directed acyclic graph is based on page resources. Tasks may comprise machine code that may be executed by hardware to perform portions of the query. These tasks may also be performed in software or relate to I/O.

Abstract: The present invention comprises a dual-use form factor for rack mounting equipment. In particular, the form-factor is configured so that it can be both rack-mounted directly or installed within a chassis. In addition, the form-factor may comprise one or more blind-mate connector systems that are suitable for blunt-type connectors, such as PCIe connectors.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of check matrix columns is generated, where each check matrix column includes a matrix having a subset of the set of primitive elements. A check matrix is generated from a subset of the set of check matrix columns, where the check matrix yields a syndrome that comprises an error pattern for the word. The check matrix is reported.

Abstract: Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A storage resource identifier corresponding to the target identifier is determined according to a forwarding table. A sequence identifier is associated with the source identifier, where the sequence identifier corresponds to the target. The source identifier and the sequence identifier are recorded at a context table, and the data packet is routed according to the storage resource identifier.

Abstract: Switching data packets includes forwarding first data packets to a first port that is associated with a first domain. Second data packets are forwarded to a second port that is associated with a second domain. The first data packets are managed using a first management subsystem of a service processor card, and the second data packets are managed using a second management subsystem of the service processor card.

Abstract: Embodiments of the present invention provide processing elements that are capable of performing high level database operations in hardware based on machine code instructions. These processing elements employ a dataflow architecture that operates on data in hardware without interruption or software. A scanning/indexing processing element may comprise logic that analyze database column groups stored in local memory, perform parallel field extraction and comparison, and generates a list of row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy an applied predicate. The scanning/indexing processing may also be used to project database column groups, search and join index structures, and manipulate in-flight metadata flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.

Abstract: Embodiments of the present invention provide a database system that is optimized by using hardware acceleration. The system may be implemented in several variations to accommodate a wide range of queries and database sizes. In some embodiments, the system may comprise a host system that is coupled to one or more hardware accelerator components. The host system may execute software or provide an interface for receiving queries. The host system analyzes and parses these queries into tasks. The host system may then select some of the tasks and translate them into machine code instructions, which are executed by one or more hardware accelerator components. The tasks executed by hardware accelerators are generally those tasks that may be repetitive or processing intensive. Such tasks may include, for example, indexing, searching, sorting, table scanning, record filtering, and the like.

Abstract: Routing a data packet includes receiving at a switch a data packet from a storage client. The data packet is associated with a destination identifier identifying a virtual target, where the virtual target is accessible by the storage client. A storage resource identifier corresponding to the destination identifier is determined according to a forwarding table at the switch. The data packet is routed according to the storage resource identifier.

Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

Abstract: A unified networking device communicates directly with storage devices and servers in the data center and communicates directly with switches and routers outside of the data center environment. The unified networking device manages data transfers between storage devices, between a storage device and a server, between a storage device and a web switch, and between a storage device and a router. The unified networking device is configured to perform data transfers while bypassing a server. The unified networking device is further configured to perform multi-protocol conversion.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: Converting data signals includes determining whether a coupled interface converter paddle coupled to a serdes is a first interface converter paddle or a second interface converter paddle. The first interface converter paddle is associated with a first communication protocol, and the second interface converter paddle is associated with a second communication protocol. The communication protocol associated with the coupled interface converter paddle is identified. Data signals are received from the coupled interface converter paddle, and deserialized according to the identified communication protocol.

Abstract: A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal.

Abstract: A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.

Abstract: Processing a data packet in a multiple protocol system area network is disclosed. A paddle card comprising a first paddle card that supports a first communication protocol or a second paddle card that supports a second communication protocol is received. The communication protocol supported by the received paddle card is identified. Data packets from the received paddle card are processed according to the identified communication protocol.

Abstract: A device for ensuring reliable data packet throughput in a redundant system includes a splitter that creates copies of a data packet and sends each copy to a separate intermediate source for processing, parallel buffers for receiving the processed packets from the intermediate sources, and a comparator for determining whether the data packets are equivalent.

Abstract: Generating a check matrix includes defining a set of column vectors. A matrix operable to have a plurality of entries is initiated. Each entry has a submatrix that includes a function of a subset of the set of column vectors. The following is repeated until a last entry of the matrix is reached. Subsets of the set of column vectors are generated from the set of column vectors, and an entry is generated from each subset. A weight associated with each entry is calculated, and an entry having a minimum weight is selected. The selected entry is added to the matrix, and the subset of column vectors associated with the selected entry is removed from the set of column vectors. The matrix is reported.