Patents by Inventor Joseph Jeddeloh

Joseph Jeddeloh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9019779
    Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Terry R. Lee, Joseph Jeddeloh
  • Patent number: 8788765
    Abstract: A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory is separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20140029325
    Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.
    Type: Application
    Filed: October 4, 2013
    Publication date: January 30, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Terry R. Lee, Joseph Jeddeloh
  • Patent number: 8564602
    Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: October 22, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Joseph Jeddeloh
  • Patent number: 8127081
    Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: February 28, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Terry R. Lee, Joseph Jeddeloh
  • Publication number: 20110032261
    Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.
    Type: Application
    Filed: July 22, 2010
    Publication date: February 10, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Joseph Jeddeloh
  • Patent number: 7777752
    Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: August 17, 2010
    Assignee: Round Rock Research, LLC
    Inventor: Joseph Jeddeloh
  • Publication number: 20090187714
    Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
    Type: Application
    Filed: August 4, 2008
    Publication date: July 23, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Terry R. Lee, Joseph Jeddeloh
  • Publication number: 20080098253
    Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.
    Type: Application
    Filed: December 12, 2007
    Publication date: April 24, 2008
    Inventors: Terry Lee, Kevin Ryan, Joseph Jeddeloh
  • Publication number: 20080016401
    Abstract: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.
    Type: Application
    Filed: September 17, 2007
    Publication date: January 17, 2008
    Applicant: Micro Technology, Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20070300105
    Abstract: A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command, address, and data signals in accordance with the test command packets, and the memory device command, address, and data signals are provided to a memory device under test that is coupled to the memory hub responsive to a memory device clock signal having a memory device clock frequency.
    Type: Application
    Filed: July 24, 2007
    Publication date: December 27, 2007
    Applicant: Micron Technology Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20070271435
    Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 22, 2007
    Inventors: Joseph Jeddeloh, Terry Lee
  • Publication number: 20070200579
    Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host.
    Type: Application
    Filed: April 6, 2007
    Publication date: August 30, 2007
    Applicant: Micron Technology, Inc.
    Inventors: Joseph Jeddeloh, Robert Totorica
  • Patent number: 7260685
    Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Terry R. Lee, Joseph Jeddeloh
  • Publication number: 20070180171
    Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
    Type: Application
    Filed: March 29, 2007
    Publication date: August 2, 2007
    Applicant: Micron Technology, Inc.
    Inventors: Joseph Jeddeloh, Ralph James
  • Publication number: 20070174562
    Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.
    Type: Application
    Filed: March 30, 2007
    Publication date: July 26, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20070168616
    Abstract: A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system controller includes a system memory controller coupled to the system memory, a processor interface coupled to the processor and an embedded cache memory integrated with the memory controller and the processor interface. The cache memory includes at least one DRAM array, at least one tag memory, and at least one cache memory controller. The cache memory controller initiates an access to either or both the DRAM array and the tag memory, as well as the system memory, before the cache memory controller has determined if the access will result in a cache hit or a cache miss. If the cache memory controller determines that the access will result in a cache hit, data are coupled from the DRAM array to the processor. If the cache memory controller determines that the access will result in a cache miss, data are coupled from the system memory to the processor.
    Type: Application
    Filed: February 16, 2007
    Publication date: July 19, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20070168595
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Application
    Filed: March 7, 2007
    Publication date: July 19, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20070113027
    Abstract: A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory are separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by independently halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively.
    Type: Application
    Filed: January 4, 2007
    Publication date: May 17, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Joseph Jeddeloh
  • Publication number: 20070101075
    Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requesters in the order in which the read requests were originally received.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 3, 2007
    Inventor: Joseph Jeddeloh