Abstract: The present invention is uniquely designed to interact with web retailer's customers with real agent reaction times as they give astute answers directly concerning web retailer's products and goals. The entire process is manageable through a third-party website which includes scripting, settings and other parameters selected by the web retailer. An artificial intelligence engine uses the combination of Bayesian probability keyword selection, natural language parsing and regular expression processing. The technology updates its response database with every client interaction-learning always takes place as it simulates a live agent, in real time. Every client interaction is recorded and analyzed, and as a result of the analysis the changes in the answer database are made.

Abstract: The present invention is uniquely designed to interact with web retailer's customers with real agent reaction times as they give astute answers directly concerning web retailer's products and goals. The entire process is manageable through a third-party website which includes scripting, settings and other parameters selected by the web retailer. An artificial intelligence engine uses the combination of Bayesian probability keyword selection, natural language parsing and regular expression processing. The technology updates its response database with every client interaction-learning always takes place as it simulates a live agent, in real time. Every client interaction is recorded and analyzed, and as a result of the analysis the changes in the answer database are made.

Abstract: The present invention is uniquely designed to interact with web retailer's customers with real agent reaction times as they give astute answers directly concerning web retailer's products and goals. The entire process is manageable through a third-party website which includes scripting, settings and other parameters selected by the web retailer. An artificial intelligence engine uses the combination of Bayesian probability keyword selection, natural language parsing and regular expression processing. The technology updates its response database with every client interaction-learning always takes place as it simulates a live agent, in real time. Every client interaction is recorded and analyzed, and as a result of the analysis the changes in the answer database are made.

Abstract: The present invention is uniquely designed to interact with web retailer's customers with real agent reaction times as they give astute answers directly concerning web retailer's products and goals. The entire process is manageable through a third-party website which includes scripting, settings and other parameters selected by the web retailer. An artificial intelligence engine uses the combination of Bayesian probability keyword selection, natural language parsing and regular expression processing. The technology updates its response database with every client interaction-learning always takes place as it simulates a live agent, in real time. Every client interaction is recorded and analyzed, and as a result of the analysis the changes in the answer database are made.

Abstract: A method is illustrated in the flow diagram 100 of FIG. 1. A processor 1001 renders a message 1025 for the processor operator's education during times of processor latency 1015, such as dialing onto any network, such as the Internet. This wait time 1017 is normally non-productive, and therefore can be used in such a way as to be non-invasive. It is also understood that this time is short, so as to make other actions, such as getting up from the desk, not attractive. Finally, even if the wait time was, or became, very short, the present invention provides the first message 1025 to the process operator that has been filtered. This filtering is a balance of the message owner's willingness to out bid other messages, the time of the day, the location of the operator, and finally the operator's likes and dislikes.

Abstract: A method to present auxiliary lighting for enhancing a scene during a multimedia presentation. The method in photonic enclosure comprising the steps of: coupling one or more illumination sources over a network, so that at least one illumination source of the one or more illumination sources is capable of being uniquely addressed; displaying a multimedia presentation; reading a series of preprogrammed illumination identifiers stored in computer readable medium corresponding with the primary multimedia presentation; interpreting one or more illumination identifiers to set one or more illumination sources for a period of time and to set the address of at least one of the one or more illumination sources; and sending a set signal in response to the interpretation of the one more illumination identifiers to one or more illumination sources over the network. In another embodiment, a gaming helmet is disclosed as the photonic enclosure used to carry out the above method.

Abstract: A semiconductor die carrier configured to be secured to a printed circuit board includes an insulative package for housing a semiconductor die. The insulative package has a top surface, a bottom surface, and a plurality of side surfaces coupling the top surface and the bottom surface. At least one row of electrically conductive leads extends from at least one of the side surfaces of the insulative package. Each of the leads has a proximal end, at least one horizontal portion extending in a horizontal direction, at least one vertical portion extending in a vertical direction, and a distal end. The distal ends of the leads are configured to be secured to the printed circuit board such that, when the distal ends of the leads are secured to the printed circuit board, at least a portion of the insulative package is located below an upper surface of the printed circuit board.

Abstract: A semiconductor die carrier includes an insulative module; a plurality of electrically conductive leads extending from the insulative module; a semiconductor die housed with the insulative module; and at least one high frequency capacitor secured to the insulative module for facilitating transmission of high frequency signals carried to and from the semiconductor die on the electrically conductive leads.

Abstract: A network protection method and apparatus are disclosed for alerting an operator when a terminal device is disconnected from the network. A network controller adapter is connected to a network control computer. The network controller periodically stops normal data communication and scans some or all of the network ports to ascertain the present and absent status of a terminal device at each port. Status is detected by passing a current through a port and measuring the feedback voltage. If the status changes between scans, an operator is alerted by sounding an alarm at the network control computer or by other steps such as dialing a telephone number and transmitting a stored message or by transmitting an alarm message over the network to one of the terminal devices such as a personal computer.

Abstract: A flexible cable assembly for coupling an electronic apparatus, having a port for receiving personal computer cards in accordance with the PCMCIA standard, to at least one peripheral device, said flex cable assembly comprises a personal computer card connector, in accordance with the PCMCIA standard, for connecting into a corresponding port in the electronic apparatus, and a flexible cable connected to the personal computer card connector. The personal computer card connector also comprises an interface to said at least one peripheral device. In accordance with a further aspect of the invention, the flex cable assembly can also couple a first electronic apparatus, to a second electronic apparatus, each having a port for receiving personal computer cards in accordance with the PCMCIA standard.

Abstract: An electrical device for logic circuits having a package comprising a combination of controlled collapse electrical interconnections, such as solder balls and pin through-hole conductors, wherein the conductors are disposed outside the perimeter of an inter-array of solder balls, which when a maximum number of solder balls are disposed, the array is circular in shape, so as to provide an increased footprint for the electrical device beyond that, otherwise maximum footprint for solder balls alone, which footprint is otherwise limited in size due to failures which occur in solder balls when solder balls are exposed to thermal and mechanical stress levels at extended distances from the neutral or zero stress point of the array.

Abstract: A thermoelectrically cooled integrated circuit package including an insulative module which defines a cavity, a thermoelectric cooler within the cavity, and an integrated circuit chip connected to the thermoelectric cooler, thus providing an integrated circuit package in which the integrated circuit package itself dissipates thermal energy generated by the integrated circuit chip.

Abstract: A thermoelectrically cooled integrated circuit package is provided which includes a thermally conductive dielectric substrate, an input connecting portion and an output connecting portion supported by the dielectric substrate, and an integrated circuit chip including an input terminal and output terminal. The input terminal is electrically connected to the input connecting portion via a first conductive material, and the output terminal is electrically connected to the output connecting portion via a second conductive material. The first conductive material and the second conductive material thermoelectrically cool the integrated circuit chip when a signal passes through the first conductive material and the second conductive material.

Abstract: Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path.

Abstract: A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.

Abstract: A voltage controlled oscillator is formed of a plurality of cascaded inverter stages in a ring configuration. Each inverter stage is a grounded emitter circuit having an active pull-up stage in order to achieve a short stage delay. The frequency of the ring oscillator is determined by the number of inverter stages, and the gain is selectable by coupling an external control voltage to only certain of the inverters. The VCO may be fabricated on a single integrated circuit along with the other circuits necessary to form a phase locked loop or other frequency generation system.

Abstract: A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory is designed to utilize an externally generated address valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/reset latch and starts the memory. The addressed memory cells are sensed. When at least one memory cell has data at its output below a threshold, the data are said to be unstable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits are stable, a signal is sent to the set/reset latch to cause it to be reset. The resetting of the set/reset latch causes an output thereof to change state. This state change comprises the read complete signal which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.

Abstract: A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and in particular the write operation thereof.

Abstract: A random access read/write memory array utilizing unclamped complementary transistor current switch (CTS) memory cells and having m columns and n rows. Each of the m columns of memory cells connected between the bit lines of a discrete one of m pairs of bit lines. Each of the n rows of memory cells connected between the word line and drain line of a discrete one of n pairs of word-drain lines. N identical write enhancement circuit means for enhancing the write operation of the memory array employing unclamped CTS memory cells. The write enhancement circuit means is preferably a single PN diode, or diode connected transistor, connected across each word/drain pair.