Patents by Inventor Ju-Li Huang
Ju-Li Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200044073Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.Type: ApplicationFiled: February 27, 2019Publication date: February 6, 2020Applicant: Taiwam Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li HUANG, Chun-Sheng Liang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang, Chun-Ming Yang, Yu-Chi Pan
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Patent number: 10541317Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.Type: GrantFiled: March 1, 2018Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
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Patent number: 10529629Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: GrantFiled: April 30, 2018Date of Patent: January 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20190385896Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang, Jeng-Ya David Yeh
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Patent number: 10490410Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.Type: GrantFiled: December 28, 2018Date of Patent: November 26, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20190341317Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.Type: ApplicationFiled: July 22, 2019Publication date: November 7, 2019Inventors: Ju-Li Huang, Chih-Long Chiang, Kuo Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang
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Publication number: 20190333826Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20190273149Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li HUANG, Chun-Sheng LIANG, Ming-Chi HUANG, Ming-Hsi YEH, Ying-Liang CHUANG, Hsin-Che CHIANG
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Patent number: 10361133Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.Type: GrantFiled: September 18, 2017Date of Patent: July 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Chih-Long Chiang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo Bin Huang
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Publication number: 20190164766Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.Type: ApplicationFiled: December 28, 2018Publication date: May 30, 2019Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 10283417Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further includes a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer includes metal phosphate and the second self-protective layer includes boron including complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.Type: GrantFiled: December 6, 2017Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20190131185Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further comprises a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer comprises metal phosphate and the second self-protective layer comprises boron comprising complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.Type: ApplicationFiled: November 30, 2018Publication date: May 2, 2019Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20190088556Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.Type: ApplicationFiled: September 18, 2017Publication date: March 21, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: JU-LI HUANG, CHIH-LONG CHIANG, YING-LIANG CHUANG, MING-HSI YEH, KUO BIN HUANG
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Patent number: 10170317Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.Type: GrantFiled: September 28, 2017Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 9761684Abstract: A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a gate dielectric layer over the substrate, a barrier layer over the gate dielectric layer, an oxide layer over the barrier layer, and a work function metal layer over the oxide layer.Type: GrantFiled: August 30, 2016Date of Patent: September 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ju-Li Huang, Chao-Cheng Chen, Calvin Chiang, Ming-Chia Tai, Ming-Hsi Yeh
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Publication number: 20160372565Abstract: A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a gate dielectric layer over the substrate, a barrier layer over the gate dielectric layer, an oxide layer over the barrier layer, and a work function metal layer over the oxide layer.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Inventors: Ju-Li Huang, Chao-Cheng Chen, Chih-Long Chiang, Ming-Chia Tai, Ming-Hsi Yeh
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Patent number: 9431304Abstract: A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed over the substrate, and a structure surrounding the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a trench in the structure. The method further includes forming a gate dielectric layer in the trench; forming a barrier layer over the gate dielectric layer; forming an oxide layer over the barrier layer; and forming a work function metal layer over the oxide layer. In embodiments, the method further includes removing the work function metal layer by an etchant containing phosphoric acid, wherein the oxide layer prevents the etchant from etching the barrier layer.Type: GrantFiled: December 22, 2014Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ju-Li Huang, Calvin Chiang, Ming-Chia Tai, Ming-Hsi Yeh, Chao-Cheng Chen
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Publication number: 20160181163Abstract: A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed over the substrate, and a structure surrounding the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a trench in the structure. The method further includes forming a gate dielectric layer in the trench; forming a barrier layer over the gate dielectric layer; forming an oxide layer over the barrier layer; and forming a work function metal layer over the oxide layer. In embodiments, the method further includes removing the work function metal layer by an etchant containing phosphoric acid, wherein the oxide layer prevents the etchant from etching the barrier layer.Type: ApplicationFiled: December 22, 2014Publication date: June 23, 2016Inventors: Ju-Li Huang, Calvin Chiang, Ming-Chia Tai, Ming-Hsi Yeh, Chao-Cheng Chen