Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A semiconductor package comprising a main semiconductor chip having a first thickness, at least one semiconductor device on one side of the main semiconductor chip and having a second thickness less than the first thickness, a first molding layer that covers the main semiconductor chip and the semiconductor device so as to expose a top surface of the semiconductor device and to expose a top surface and a portion of a lateral surface of the main semiconductor chip, a first redistribution substrate below the first molding layer, a second redistribution substrate on the first molding layer, and a mold via that penetrates the first molding layer and connects the first redistribution substrate to the second redistribution substrate.

Abstract: A semiconductor package includes a substrate having opposite first and second surfaces; (1-1)-th substrate pads and (1-2)-th substrate pads on the first surface of the substrate; first connecting terminals on the (1-1)-th substrate pads and the (1-2)-th substrate pads; (2-1)-th substrate pads and (2-2)-th substrate pads on the second surface of the substrate; an interposer on the second surface of the substrate; second connecting terminals between the (2-1)-th substrate pads, the (2-2)-th substrate pads, and the interposer; and a first semiconductor chip on the interposer. The (1-2)-th substrate pads have a smaller maximum width than the (1-1)-th substrate pads. The (2-2)-th substrate pads have a smaller maximum width than the (2-1)-th substrate pads. The (1-1)-th substrate pads and the (2-1)-th substrate pads transmit first signals, ground signals, or power signals. The (1-2)-th substrate pads and the (2-2)-th substrate pads transmit second signals that are faster than the first signals.

Abstract: A semiconductor package including: a package substrate; an interposer on the package substrate; a chip stack on the interposer, the chip stack including a plurality of first semiconductor chips that are stacked in a first direction; a second semiconductor chip on the interposer and spaced apart from the chip stack in a second direction intersecting the first direction; and a first signal pad, a second signal pad, and a power/ground pad on a top surface of the interposer, wherein the chip stack is mounted on the first signal pad, wherein the second semiconductor chip is mounted on the second signal pad, wherein the chip stack and the second semiconductor chip are connected to the power/ground pad, and wherein the power/ground pad overlaps a portion of the chip stack and a portion of the second semiconductor chip.

Abstract: A semiconductor package includes: a first wiring structure including a first wiring layer, and a second wiring layer disposed on the first wiring layer, and connected to a first connecting structure placed disposed on the first wiring layer; a first semiconductor chip disposed on the first wiring structure and connected to the first wiring structure through a first connecting pad disposed on a first side of the first semiconductor chip; a second wiring structure disposed on the first semiconductor chip; and an insulating member disposed between the first and second wiring structures, wherein the first wiring structure further includes a first signal pattern that is electrically connected to the first connecting pad, and the first signal pattern redistributes the first connecting pad to the first connecting structure via the insulating member.

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.