Patents by Inventor Juan J. Noguera Serra

Juan J. Noguera Serra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11443091
    Abstract: An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 13, 2022
    Assignee: Xilinx, Inc.
    Inventors: Peter McColgan, Baris Ozgul, David Clarke, Tim Tuan, Juan J. Noguera Serra, Goran H. K. Bilski, Jan Langer, Sneha Bhalchandra Date, Stephan Munz, Jose Marques
  • Publication number: 20220283963
    Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Inventors: Juan J. NOGUERA SERRA, Goran Hk BILSKI, Baris OZGUL, Jan LANGER
  • Publication number: 20220283985
    Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Inventors: Goran Hk BILSKI, Juan J. NOGUERA SERRA, Baris OZGUL, Jan LANGER, David CLARKE, Sneha Bhalchandra DATE
  • Patent number: 11379389
    Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 5, 2022
    Assignee: XILINX, INC.
    Inventors: Juan J. Noguera Serra, Goran H K Bilski, Baris Ozgul, Jan Langer
  • Patent number: 11372803
    Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 28, 2022
    Assignee: XILINX, INC.
    Inventors: Goran H. K. Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, David Clarke, Sneha Bhalchandra Date
  • Publication number: 20220197846
    Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Applicant: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan, Sridhar Subramanian
  • Patent number: 11336287
    Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 17, 2022
    Assignee: Xilinx, Inc.
    Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
  • Patent number: 11323391
    Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 3, 2022
    Assignee: XILINX, INC.
    Inventors: Peter McColgan, David Clarke, Goran Hk Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Tim Tuan
  • Patent number: 11296707
    Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 5, 2022
    Assignee: Xilinx, Inc.
    Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
  • Publication number: 20220100691
    Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan, Sridhar Subramanian
  • Patent number: 11288222
    Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan, Sridhar Subramanian
  • Publication number: 20220015588
    Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.
    Type: Application
    Filed: September 7, 2021
    Publication date: January 20, 2022
    Inventors: Peter MCCOLGAN, Goran Hk BILSKI, Juan J. NOGUERA SERRA, Jan LANGER, Baris OZGUL, David CLARKE
  • Patent number: 11113223
    Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 7, 2021
    Assignee: XILINX, INC.
    Inventors: Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul, David Clarke
  • Patent number: 11061673
    Abstract: An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 13, 2021
    Assignee: XILINX, INC.
    Inventors: Baris Ozgul, Jan Langer, Juan J. Noguera Serra, Goran H. K. Bilski, Richard L. Walke
  • Patent number: 11063594
    Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Patent number: 11016822
    Abstract: Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: May 25, 2021
    Assignee: XILINX, INC.
    Inventors: Goran H. K. Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul, Richard L. Walke
  • Patent number: 10990552
    Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Goran Hk Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Philip B. James-Roxby, Christopher H. Dick
  • Patent number: 10866753
    Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 15, 2020
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Tim Tuan, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, David Clarke
  • Patent number: 10824584
    Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: November 3, 2020
    Assignee: XILINX, INC.
    Inventors: Juan J. Noguera Serra, Sneha Bhalchandra Date, Jan Langer, Baris Ozgul, Goran H K Bilski
  • Patent number: 10747531
    Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 18, 2020
    Assignee: XILINX, INC.
    Inventors: Jan Langer, Baris Ozgul, Juan J. Noguera Serra, Goran HK Bilski, Tim Tuan