Patents by Inventor Judy H. Huang
Judy H. Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8809161Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: July 3, 2013Date of Patent: August 19, 2014Assignee: Novellus Systems, Inc.Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Publication number: 20140017904Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: ApplicationFiled: July 3, 2013Publication date: January 16, 2014Inventors: Vishal GAURI, Raashina HUMAYUN, Chi-I LANG, Judy H. HUANG, Michael BARNES, Sunil SHANKER
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Patent number: 8580697Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.Type: GrantFiled: February 18, 2011Date of Patent: November 12, 2013Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 8481403Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: January 4, 2011Date of Patent: July 9, 2013Assignee: Novellus Systems, Inc.Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 8183150Abstract: The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.Type: GrantFiled: October 24, 2008Date of Patent: May 22, 2012Assignee: Applied Materials, Inc.Inventors: Judy H. Huang, Christopher Dennis Bencher, Sudha Rathi, Christopher S. Ngai, Bok Hoen Kim
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Patent number: 7915139Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.Type: GrantFiled: July 23, 2009Date of Patent: March 29, 2011Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 7888233Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: March 25, 2009Date of Patent: February 15, 2011Assignee: Novellus Systems, Inc.Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 7727906Abstract: This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.Type: GrantFiled: July 26, 2006Date of Patent: June 1, 2010Assignee: Novellus Systems, Inc.Inventors: Sunil Shanker, Chi-I Lang, Minh Anh Nguyen, Judy H. Huang
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Patent number: 7670945Abstract: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s).Type: GrantFiled: December 29, 2008Date of Patent: March 2, 2010Assignee: Applied Materials, Inc.Inventor: Judy H. Huang
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Patent number: 7582555Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.Type: GrantFiled: December 29, 2005Date of Patent: September 1, 2009Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Publication number: 20090130837Abstract: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s).Type: ApplicationFiled: December 29, 2008Publication date: May 21, 2009Inventor: Judy H. Huang
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Patent number: 7524735Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: June 5, 2006Date of Patent: April 28, 2009Assignee: Novellus Systems, IncInventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Publication number: 20090050902Abstract: The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.Type: ApplicationFiled: October 24, 2008Publication date: February 26, 2009Inventors: Judy H. Huang, Christopher Dennis Bencher, Sudha Rathi, Christopher S. Ngai, Bok Hoen Kim
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Patent number: 7482245Abstract: High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.Type: GrantFiled: June 20, 2006Date of Patent: January 27, 2009Assignee: Novellus Systems, Inc.Inventors: Jengyi Yu, Chi-I Lang, Judy H. Huang
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Patent number: 7476621Abstract: Plasma etch processes incorporating H2/Noble gas etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen and one or more Noble gases as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.Type: GrantFiled: March 1, 2006Date of Patent: January 13, 2009Assignee: Novellus Systems, Inc.Inventors: Minh Anh Nguyen, Chi-I Lang, Wenxian Zhu, Judy H. Huang
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Patent number: 7470611Abstract: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The dielectric layer can be deposited with different precursors as the SiC material, but preferably with the same or similar precursors as the SiC material. The present invention is particularly useful for ICs using high diffusion copper as a conductive material. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features.Type: GrantFiled: December 12, 2005Date of Patent: December 30, 2008Assignee: Applied Materials, Inc.Inventor: Judy H. Huang
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Patent number: 7344996Abstract: Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.Type: GrantFiled: June 22, 2005Date of Patent: March 18, 2008Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Wenxian Zhu, Ratsamee Limdulpaiboon, Judy H. Huang
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Patent number: 7227244Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: August 24, 2004Date of Patent: June 5, 2007Assignee: Applied Materials, Inc.Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 7211525Abstract: Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.Type: GrantFiled: March 16, 2005Date of Patent: May 1, 2007Assignee: Novellus Systems, Inc.Inventors: Sunil Shanker, Sean Cox, Chi-I Lang, Judy H. Huang, Minh Anh Nguyen, Ken Vo, Wenxian Zhu
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Patent number: 7070657Abstract: This invention provides a stable process for depositing an antireflective layer. Helium gas is used to lower the deposition rate of plasma-enhanced silane oxide, silane oxynitride, and silane nitride processes. Helium is also used to stabilize the process, so that different films can be deposited. The invention also provides conditions under which process parameters can be controlled to produce antireflective layers with varying optimum refractive index, absorptive index, and thickness for obtaining the desired optical behavior.Type: GrantFiled: October 15, 1999Date of Patent: July 4, 2006Assignee: Applied Materials Inc.Inventors: David Cheung, Joe Feng, Judy H. Huang, Wai-Fan Yau