Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.

Abstract: A semiconductor device includes a charge-absorbing structure disposed over a substrate; an insulating layer disposed over the charge-absorbing structure; a semiconductor layer disposed over the insulating layer; a plurality of first doped regions and a plurality of second doped regions disposed in the semiconductor layer, wherein the first doped regions and second doped regions extend in a first direction and are alternately arranged along a second direction that is different than the first direction, and the plurality of first doped regions and the plurality of second doped regions have different conductivity types; a source and a drain disposed respectively on opposite sides of the plurality of first doped regions and the plurality of second doped regions and extend in the second direction; and a gate disposed on the plurality of first doped regions and the plurality of second doped regions and extends in the second direction.

Abstract: A semiconductor device includes a charge-absorbing structure disposed over a substrate; an insulating layer disposed over the charge-absorbing structure; a semiconductor layer disposed over the insulating layer; a plurality of first doped regions and a plurality of second doped regions disposed in the semiconductor layer, wherein the first doped regions and second doped regions extend in a first direction and are alternately arranged along a second direction that is different than the first direction, and the plurality of first doped regions and the plurality of second doped regions have different conductivity types; a source and a drain disposed respectively on opposite sides of the plurality of first doped regions and the plurality of second doped regions and extend in the second direction; and a gate disposed on the plurality of first doped regions and the plurality of second doped regions and extends in the second direction.

Abstract: An inflatable shoe stretcher includes a bag body that is formed by coupling outer peripheries of two bag sheets and that defines an air-filling space therein, an one-way air inflow unit that is mounted between the bag sheets for filling air into the air-filling space, and a heat-sealed unit that is formed by coupling portions of the bag sheets. The heat-sealed unit includes two main heat-sealed subunits for segregating the air-filling space into three air-filling space portions. The bag body is able to be bent alongside the main heat-sealed subunits when the air-filling space portions are filled with air.

Abstract: An inductor structure is provided. The inductor structure includes a substrate, a first dielectric layer formed on the substrate, a first metal layer formed in the first dielectric layer, a second dielectric layer formed on the first dielectric layer, a second metal layer formed in the second dielectric layer, at least one intermediate dielectric layer formed between the first and second dielectric layers, at least one intermediate metal layer formed in the intermediate dielectric layer, and a plurality of vias connected to the first metal layer and the intermediate metal layer. The vias are connected to the second metal layer and the intermediate metal layer. The first metal layer, the vias, the intermediate metal layer, and the second metal layer form an extension path which extends in a spiral mode.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A semiconductor structure includes an insulating layer, a semiconductor layer, and an epitaxial layer. The insulating layer is disposed on a substrate. The semiconductor layer is disposed on the insulating layer. The semiconductor layer includes a first buried layer and a second buried layer. The first buried layer has a first conductivity type. The second buried layer is disposed over the first buried layer and has a second conductivity type opposite to the first conductivity type. The second buried layer has at least two portions separate from each other. The epitaxial layer is disposed on the semiconductor layer.

Abstract: A semiconductor device includes a substrate, a semiconductor layer, a doped region, a device region, a first isolation structure, a second isolation structure and a terminal. The semiconductor layer is disposed over the substrate. The doped region is disposed in the semiconductor layer. The device region is disposed on the doped region and includes a source, a drain and a gate. The first isolation structure is disposed in the semiconductor layer and surrounds the doped region. The second isolation structure surrounds the first isolation structure and is spaced apart from the first isolation structure. The terminal is disposed between the first isolation structure and the second isolation structure, and is equipotential with the source.

Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.

Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.

Abstract: A semiconductor device including a substrate having an active region and a field-plate region therein is disclosed. At least one trench-gate structure is in the substrate. The field-plate region is at a first side of the trench-gate structure. At least one source doped region is in the substrate at a second side opposite to the first side of the trench-gate structure. The source doped region adjoins the sidewall of the trench-gate structure. A drain doped region is in the substrate corresponding to the active region. The field-plate region is between the drain doped region and the trench-gate structure. An extending direction of length of the trench-gate structure is perpendicular to that of the drain doped region as viewed from a top-view perspective.

Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.