Patents by Inventor Jui-Feng Kuan

Jui-Feng Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200342156
    Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.
    Type: Application
    Filed: July 15, 2020
    Publication date: October 29, 2020
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Publication number: 20200285796
    Abstract: A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Chi-Wen CHANG, Jui-Feng KUAN
  • Patent number: 10763253
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10719652
    Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Patent number: 10685161
    Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Wen Chang, Jui-Feng Kuan
  • Publication number: 20200175219
    Abstract: A method is disclosed herein. The method includes: adjusting first parameters associated with parameterized cells in a netlist of an integrated circuit (IC) to generate second parameters associated with the parameterized cells in the netlist of the IC; updating the netlist of the IC according to the second parameters; and performing a simulation according to the netlist.
    Type: Application
    Filed: November 22, 2019
    Publication date: June 4, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Yu YANG, Ren-Hong FU, Chin-Cheng KUO, Jui-Feng KUAN
  • Publication number: 20200151382
    Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
  • Patent number: 10634972
    Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hui-Yu Lee, Jui-Feng Kuan
  • Publication number: 20200125696
    Abstract: A method includes assigning a default voltage value of a voltage domain in an integrated circuit (IC) schematic to a net in the voltage domain, generating a simulation voltage value of the net by performing a circuit simulation on the net, and modifying the IC schematic to include a voltage value associated with the net, based on the simulation voltage value of the net.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 23, 2020
    Inventors: Chi-Wen CHANG, Jui-Feng KUAN
  • Publication number: 20200057834
    Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.
    Type: Application
    Filed: November 29, 2018
    Publication date: February 20, 2020
    Inventors: Chi-Wen CHANG, Jui-Feng KUAN
  • Patent number: 10540475
    Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Publication number: 20200006325
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10509883
    Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
  • Publication number: 20190325105
    Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Patent number: 10346576
    Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Publication number: 20190129272
    Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 2, 2019
    Inventors: Hui-Yu LEE, Jui-Feng KUAN
  • Publication number: 20190034578
    Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.
    Type: Application
    Filed: October 2, 2018
    Publication date: January 31, 2019
    Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
  • Publication number: 20180373113
    Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 27, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Yu LEE, Jui-Feng KUAN
  • Patent number: 10162244
    Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Yu Lee, Jui-Feng Kuan
  • Patent number: 10163787
    Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Yi-Kan Cheng