Patents by Inventor Jui-Feng Kuan
Jui-Feng Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200006325Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
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Patent number: 10509883Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: GrantFiled: January 24, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
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Publication number: 20190325105Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
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Patent number: 10346576Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.Type: GrantFiled: July 26, 2018Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
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Publication number: 20190129272Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.Type: ApplicationFiled: December 17, 2018Publication date: May 2, 2019Inventors: Hui-Yu LEE, Jui-Feng KUAN
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Publication number: 20190034578Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.Type: ApplicationFiled: October 2, 2018Publication date: January 31, 2019Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
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Publication number: 20180373113Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.Type: ApplicationFiled: July 28, 2017Publication date: December 27, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hui-Yu LEE, Jui-Feng KUAN
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Patent number: 10162244Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.Type: GrantFiled: July 28, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Yu Lee, Jui-Feng Kuan
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Patent number: 10163787Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.Type: GrantFiled: June 30, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Yi-Kan Cheng
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Patent number: 10157252Abstract: An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first inter layer via (ILV) to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for engineering change order (ECO) purpose.Type: GrantFiled: May 13, 2016Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20180330036Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.Type: ApplicationFiled: July 26, 2018Publication date: November 15, 2018Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
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Patent number: 10095827Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.Type: GrantFiled: April 2, 2018Date of Patent: October 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
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Patent number: 10083257Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.Type: GrantFiled: August 20, 2014Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Cheng Kuo, Wei Min Chan, Wei-Yu Hu, Jui-Feng Kuan
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Publication number: 20180225407Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.Type: ApplicationFiled: April 2, 2018Publication date: August 9, 2018Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
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Patent number: 10042967Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.Type: GrantFiled: September 21, 2016Date of Patent: August 7, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
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Patent number: 9996643Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.Type: GrantFiled: November 17, 2014Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Sheng Chen, Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Ching-Shun Yang
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Publication number: 20180150585Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: ApplicationFiled: January 24, 2017Publication date: May 31, 2018Inventors: Tsun-Yu YANG, Wei-Yi HU, Jui-Feng KUAN, Hsien-Hsin Sean LEE, Po-Cheng PAN, Hung-Wen HUANG, Hung-Ming CHEN, Abhishek PATYAL
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Patent number: 9934352Abstract: A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC.Type: GrantFiled: November 13, 2015Date of Patent: April 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20170358572Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.Type: ApplicationFiled: August 28, 2017Publication date: December 14, 2017Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20170300611Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.Type: ApplicationFiled: June 30, 2017Publication date: October 19, 2017Inventors: Hui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Yi-Kan CHENG