Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having multiple structures. Each of the structures includes an active region isolated by trenches in the substrate, an insulating layer on the active region, and a hardmask layer on the insulating layer. The method also includes performing a first ion implantation into a first structure configured to form a first type device, performing a pull-back process on the hardmask layer and on the insulating layer of the first structure to form a receded hardmask layer and a receded insulating layer and expose a corner portion of the active region, and performing a rounding process on the exposed corner portion. The rounded corner portion of the active region has an increased curvature radius that reduces the concentration of the electric field and improves the reliability of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having multiple structures. Each of the structures includes an active region isolated by trenches in the substrate, an insulating layer on the active region, and a hardmask layer on the insulating layer. The method also includes performing a first ion implantation into a first structure configured to form a first type device, performing a pull-back process on the hardmask layer and on the insulating layer of the first structure to form a receded hardmask layer and a receded insulating layer and expose a corner portion of the active region, and performing a rounding process on the exposed corner portion. The rounded corner portion of the active region has an increased curvature radius that reduces the concentration of the electric field and improves the reliability of the semiconductor device.

Abstract: In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.

Abstract: A method of fabricating a flash memory. A tunneling dielectric layer, a conductive layer and a mask layer are sequentially formed on a substrate. The mask layer, the conductive layer and the tunneling dielectric layer are patterned to form longitudinally arranged strips on the substrate. Buried drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed on perimeters of the floating gate structures. The insulation layer has a top surface lower than a top surface of the conductive layer of the floating gate structures, such that a part of sidewalls of the conductive layer is exposed. The mask layer is removed, a gate dielectric layer is formed on the exposed conductive layer, and a control gate is formed on the gate dielectric layer.

Abstract: In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.

Abstract: A flash memory device that comprises a self-aligned contact opening and a fabrication method thereof are described. Subsequent to the formation of the control gate of the flash memory device, a spacer is formed over a sidewall of the gate layer in a subsequent process, followed by forming another dielectric layer over the substrate to cover the control gate. Thereafter, the dielectric layer and the dielectric layer underlying the control gate are patterned to form a self-aligned contact opening between two neighboring control gates to expose a bit line in the substrate. A conductive material further fills the self-aligned contact opening.

Abstract: The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A flash memory device that comprises a self-aligned contact opening and a fabrication method thereof are described. Subsequent to the formation of the control gate of the flash memory device, a spacer is formed over a sidewall of the gate layer in a subsequent process, followed by forming another dielectric layer over the substrate to cover the control gate. Thereafter, the dielectric layer and the dielectric layer underlying the control gate are patterned to form a self-aligned contact opening between two neighboring control gates to expose a bit line in the substrate. A conductive material further fills the self-aligned contact opening.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

Abstract: The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.